access icon free Energy-efficient VLSI implementation of multipliers with double LSB operands

© The Institution of Engineering and Technology
Received 21/03/2018, Accepted 01/04/2019, Revised 13/03/2019, Published 05/04/2019

Multiplication is an arithmetic operation that has a significant impact on the performance of various real-life applications, such as digital signal processing, image processing and computer vision. In this study, targeting to exploit the efficiency of alternative number representation formats, the authors propose an energy-efficient scheme for multiplying 2's-complement binary numbers with two least significant bits (LSBs). The double-LSB (DLSB) arithmetic delivers several benefits, such as the symmetric representation range, the number negation performed only by bitwise inversion, and the facilitation of the rounding process in the results of floating point architectures. The hardware overhead of the proposed circuit, when implemented at 45 nm, is negligible in comparison with the conventional Modified Booth multiplier for the ordinary 2's-complement numbers (3.1% area and 3.3% energy average overhead for different multiplier's bit-width). Moreover, the proposed DLSB multiplier outperforms the previous state-of-the-art implementation by providing 10.2% energy and 7.8% area average gains. Finally, they demonstrate how the DLSB multipliers can be effectively used as a building block for the implementation of larger multiplications, delivering area and energy savings.

Inspec keywords: VLSI; digital signal processing chips; multiplying circuits; floating point arithmetic

Other keywords: double-LSB arithmetic; image processing; multipliers; real-life applications; energy average overhead; multiplication; number negation; energy-efficient scheme; rounding process; number representation formats; bitwise inversion; double LSB operands; arithmetic operation; symmetric representation range; DLSB multiplier; energy-efficient VLSI implementation; energy savings; area average gains; digital signal processing; computer vision; hardware overhead; size 45.0 nm; modified booth multiplier; point architectures

Subjects: Digital signal processing chips; Logic circuits; Digital arithmetic methods; Logic and switching circuits; Digital signal processing chips

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