© The Institution of Engineering and Technology
This study presents an improved convergent distributed arithmetic (DA)based low complexity pipelined leastmeansquare filter. The concept is based on a convex combination of two adaptive filters (ADFs) where the convergence performance of the combined filter is adjusted by the stepsizes of ADFs. The proposed technique replaced two ADF units by a single unit of the DAbased ADF. Further reduction in hardware complexity is achieved by sharing the filter partial products. Moreover, a bitlevel coefficient update unit is employed to minimise its hardware complexity. In addition, a novel lowcost strategy is presented to improve the convergence performance of the proposed filter by comparing the timewindow corresponding to the maximum correlation of delayed error signals with a predefined window with n being time instant and . Compared with the best existing scheme, the proposed design offers 46.42% fewer adders, 36.69% fewer registers and 18.75% fewer multiplexers for a 64thorder filter. Application specific integrated circuit synthesis results show that the proposed design occupies 37.10% less chiparea and consumes 24.79% less power. In addition, the proposed design provides 20.35% less areadelayproduct and 4.76% less energypersample for 64th order with the fourthorder base unit over the best existing scheme.
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