Symptom reliability: S-parameters evaluation of power laterally diffused-metal–oxide–semiconductor field-effect transistor after pulsed-RF life tests for a radar application

Symptom reliability: S-parameters evaluation of power laterally diffused-metal–oxide–semiconductor field-effect transistor after pulsed-RF life tests for a radar application

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This paper treats the s-parameter performance degradation by hot electron induced for N-MOSFET devices used in radar applications. This study is relevant for devices operating in the RF frequency regime. The power LD-MOSFET device (0.8 µm channel length, Gate oxide thickness 0.065 µm and 2.2 GHz) are designed and fabricated. Subsequently, life tests in pulsed RF cause, after ageing, the electrical behaviour and its relation with charge trapping at the interface are presented and discussed. Unlike all other current methods, a complete evaluation of S parameters is carried out to obtain key information concerning the defects location. The s-parameter performance degradation can be explained by the transconductance and the miller capacitance move, and by the leakage current augmentation IG, which is shown by hot-carrier event from the Si/SiO2 interface state generation and/or in a build up of negative charge. Also, the degradation can be predicted by the experimental correlation of RF and dc performance shifts, favour by the measurement of dc performance or initial leakage current. The analysis accompanied proves that the s-parameters shift by hot electron induced and should be taken into consideration in the design. Through physical processes of ATLAS-SILVACO simulations these degradation phenomena are located and confirmed


    1. 1)
      • 1. Belaïd, M.A., Ketata, K., Gares, M., et al: ‘Analysis and simulation of self-heating effects on RF LDMOS devices’. Proc. IEEE Conf. Simulation of Semiconductor Processes and Devices SISPAD 2005, Tokyo, Japan, pp. 231234.
    2. 2)
      • 2. Belaïd, M.A., Gares, M., Daoud, K., et al: ‘Performance drifts of N-MOSFETs under pulsed RF life test’, Microelectron. Reliab., 2014, 54, pp. 18511855.
    3. 3)
      • 3. Nayak, P., Pramanick, S.K., Rajashekara, K.: ‘A high temperature gate driver for silicon carbide MOSFET’, IEEE Trans. Ind. Electron., 2018, 65, pp. 19551964.
    4. 4)
      • 4. Belaïd, M.A., Douad, K.: ‘Evaluation of hot-electron effects on critical parameter drifts in power RF LDMOS transistors’, Microelectron. Reliab., 2010, 50, pp. 17631767.
    5. 5)
      • 5. Zárate-Rincón, F., García-García, D., Vega-González, V.H., et al: ‘Characterization of hot-carrier-induced RF-MOSFET degradation at different bulk biasing conditions from S-parameters’, IEEE Trans. Microw. Theory Tech., 2016, 64, pp. 125132.
    6. 6)
      • 6. Santini, T., Sebastien, M., Florent, M.: ‘Gate oxide reliability assessment of a SiC MOSFET for high temperature aeronautic applications’. Proc. Int. Conf. ECCE Asia Downunder, Melbourne, VIC, Australia, 2013, pp. 385391.
    7. 7)
      • 7. Wilk, G.D., Wallace, R.M., Anthony, J.M.: ‘High-κ gate dielectrics: current status and materials properties considerations’, J. Appl. Phys., 2001, 89, pp. 52435275.
    8. 8)
      • 8. Lu, Q., Park, D., Kalnitsky, A., et al: ‘Leakage current comparison between ultrathin Ta2O5 films and conventional gate dielectrics’, IEEE Electron Device, 1998, 19, pp. 341342.
    9. 9)
      • 9. Yu, Z., Ramdani, J., Curless, J.A., et al: ‘Epitaxial perovskite thin films grown on silicon by molecular beam epitaxy’, J. Vac. Sci. Technol. B, Nanotechnol. Microelectron., 2000, 18, pp. 16531657.
    10. 10)
      • 10. Chin, A., Wu, Y.H., Chen, S.B., et al: ‘High quality La2O3 and Al2O3 gate dielectrics with equivalent oxide thickness’. VLSI Symp. Technical Digest, Honolulu, USA, June 2000, pp. 1617.
    11. 11)
      • 11. Belaïd, M.A., Gares, M., Daoud, K., et al: ‘Failure analysis of hot-electron effect on power RF N-LDMOS transistors’. Proc. Int. Conf. IEEE Design & Technology of Integrated Systems in Nanoscale Era, Tunis, Tunisia, 2012, pp. 16.
    12. 12)
      • 12. Jagannathan, S., Loveless, T.D., Zhang, E.X., et al: ‘Sensitivity of high-frequency RF circuits to total ionizing dose degradation’, IEEE Trans. Nucl. Sci., 2013, 60, pp. 44984504.
    13. 13)
      • 13. Lee, C.-I., Lin, Y.-T., Lin, W.-C.: ‘An improved four-port equivalent circuit model of RF MOSFETs for breakdown operation’, IEEE Trans. Device Mater. Reliab., 2015, 15, pp. 109114.
    14. 14)
      • 14. Silvaco International: ‘ATLAS user's manual-device simulation software’ (Santa Clara, CA, 1998).
    15. 15)
      • 15. Raman, A., Walker, D.G., Fisher, T.S.: ‘Simulation of non-equilibrium thermal effects in power LDMOS transistors’, Solid-State Electron., 2003, 47, pp. 12651273.
    16. 16)
      • 16. Wang, L.-S., Xu, J.-P., Liu, L., et al: ‘Influences of remote Coulomb and interface-roughness scatterings on electron mobility of InGaAs nMOSFET with high-k stacked gate dielectric’, IEEE Trans. Nanotechnol., 2015, 14, pp. 854861.
    17. 17)
      • 17. Cortes, I., Roig, J., Flores, D., et al: ‘Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile’, Microelectron. Reliab., 2005, 45, pp. 493498.
    18. 18)
      • 18. Lin, S.C., Kuo, J.B.: ‘Modeling the fringing electric field effect on the threshold voltage of FD SOI nMOS devices with the LDD/sidewall oxide spacer structure’, IEEE Trans. Electron Devices, 2003, 50, pp. 25592564.
    19. 19)
      • 19. Liu, S., Li, S., Li, Z., et al: ‘Lateral DMOS with partial-resist-implanted drift region for alleviating hot-carrier effect’, IEEE Trans. Device Mater. Reliab., 2017, 99, pp. 780784.
    20. 20)
      • 20. Hao, J., Pelletier, M., Murphy, R., et al: ‘The influence of self-heating on the measurement of hot carrier degradation in high voltage n-channel LDMOS’. Proc. Int. Conf. IEEE Reliability Physics Symp. (IRPS), Monterey, CA, USA, 2017, pp. 4144.
    21. 21)
      • 21. Lin, C.-Y., Chang, T.-C., Liu, K.-J.: ‘Analysis of contrasting degradation behaviors in channel and drift regions under hot carrier stress in PDSOI LD N-channel MOSFETs’, IEEE Electron Device Lett., 2017, 38, pp. 705707.
    22. 22)
      • 22. Crespo-Yepes, A., Barajas, E., Martin-Martinez, J.: ‘MOSFET degradation dependence on input signal power in a RF power amplifier original research article’, Microelectron. Eng., 2017, 178, pp. 289292.
    23. 23)
      • 23. Mbarek, S., Fouquet, F., Dherbecourt, P., et al: ‘Gate oxide degradation of SiC MOSFET under short-circuit ageing tests’, Microelectron. Reliab., 2016, 64, pp. 415418.

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