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access icon free Precision analysis with analytical bit-width optimisation process for linear circuits with feedbacks

Finding the best possible word length to accuracy trade off seems to be an obvious design task. However, the literature and carful design reviews show that word lengths are often overestimated to put the data accuracy at the safe side. This study proposes a mathematical process to balance that trade off. It describes an analytical optimisation technique that considers every interconnection and it shows clear improvement with respect to published results. To allow reproducibility of their work, detailed procedures are provided. Implementation results are presented for different configurations of infinite impulse response filters. More, the impact of the proposed bit-width optimisation on the filter poles and zeros is provided to show the effectiveness of the proposed solution. Their solution provides overall improvement going up to 17% of the circuit's area with respect to existing methods. The proposed technique for uniform fractional bits allocation runs in a negligible time independently of the targeted accuracy.

References

    1. 1)
      • 10. Radecka, K., Zilic, Z.: ‘Arithmetic transforms of imprecise datapaths by Taylor series conversion’. Proc. Int. Conf. Electron. Circuits System, Nice, France, 2006, pp. 696699.
    2. 2)
      • 26. Caffarena, G., Carreras, C., Lopez, J., et al: ‘SQNR estimation of fixed-point DSP algorithms’, Int. J. Adv. Signal Process., 2010, 10, pp. 111.
    3. 3)
      • 22. Pang, Y., Yan, Y., Lin, J., et al: ‘Designing optimized imprecise fixed-point arithmetic circuits specified by polynomials with various constraints’, J. −Circuits Syst. Comput., 2014, 23, p. 1450010.
    4. 4)
      • 13. Carletta, J., Veillette, R., Krach, F., et al: ‘Determining appropriate precisions for signals in fixed-point IIR filters’. Proc. Design Automation Conf., June 2003, pp. 656661.
    5. 5)
      • 11. Oppenheim, A.V., Weinstein, C.J.: ‘Effects of finite register length in digital filtering and the fast Fourier transform’. Proc. IEEE, 1972, 60, pp. 957976.
    6. 6)
      • 14. Sarbishei, O., Pang, Y., Radecka, K.: ‘Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks’. Proc. IEEE HLDVT, Anaheim, FL, USA, June 2010, pp. 2532.
    7. 7)
      • 23. Pang, Y., Radecka, K., Zilic, Z.: ‘Optimization of imprecise circuits represented by Taylor series and real-valued polynomials’, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010, 29, pp. 11771190.
    8. 8)
      • 25. López, J.A., Caffarena, G., Carreras, C., et al: ‘Fast and accurate computation of the round-off noise of linear time-invariant systems’, IET Circuits Dev. Syst., 2008, 02, pp. 393408.
    9. 9)
      • 5. Lee, D., Gaffar, A.A., Mencer, O., et al: ‘Minibit: bit-width optimization via affine arithmetic’ (DAC, Anaheim, CA, USA, 2005), pp. 837840.
    10. 10)
      • 24. Jackson, L.B.: ‘On the interaction of round-off noise and dynamic range in digital filters’, Bell Syst. Tech. J., 1970, 49, pp. 159184.
    11. 11)
      • 8. Kum, K., Sung, W.: ‘Combined word-length optimization and high level synthesis of digital signal processing systems’, IEEE Trans. Comput. Aided Design, 2001, 20, pp. 921930.
    12. 12)
      • 17. Vakili, S., Langlois, J.M.P., Bois, G.: ‘Enhanced precision analysis for accuracy-aware bit-width optimization using affine arithmetic’, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013, 32, pp. 18531865.
    13. 13)
      • 6. Osborne, W.G., Cheung, R.C.C., Coutinho, J.G.F., et al: ‘Automatic accuracy-guaranteed bit-width optimization for fixed and floating-point systems’. Proc. Int. Conf. Field Programmable Logic and Applications (FPL), Amsterdam, Netherlands, 2007, pp. 617620.
    14. 14)
      • 9. Gaffar, A., Mencer, O., Luk, W., et al: ‘Unifying bit-width optimization for fixed-point and floating-point designs’. Proc. IEEE Symp. Field-Programmable Custom Computing, Napa, CA, USA, March 2004, pp. 7988.
    15. 15)
      • 16. Lamini, E., Bellal, R., Tagzout, S., et al: ‘Enhanced bit-width optimization for linear circuits with feedbacks’. Design and Test Symp. (IDT), Algiers, Algeria, December 2014, pp. 168173.
    16. 16)
      • 3. Kinsman, A.B., Nicolici, N.: ‘Bit-width allocation for hardware accelerators for scientific computing using SAT-modulo theory’, IEEE Trans. Comput.-Aided Design, 2010, 29, pp. 405413.
    17. 17)
      • 4. Radecka, K., Zilic, Z.: ‘Using arithmetic transform for verification of datapath circuits via error modeling’. Proc. IEEE VLSI Test Symp, May 2000, pp. 271277.
    18. 18)
      • 12. Menard, D., Rocher, R., Sentieys, O.: ‘Analytical fixed-point accuracy evaluation in linear time-invariant systems’, IEEE Trans. Circuits Syst. I Regul. Pap., 2008, 55, pp. 31973208.
    19. 19)
      • 15. Sarbishei, O., Radecka, K., Zilic, Z.: ‘Analytical optimization of bit-widths in fixed-point LTI systems’, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012, 31, pp. 343355.
    20. 20)
      • 18. Chichyang, C.: ‘High-order Taylor series approximation for efficient computation of elementary functions’, IET Comput. Digit. Tech., 2015, 9, pp. 328335.
    21. 21)
      • 20. Mahdieh, G., Alizadeh, B., Forouzandeh, B.: ‘Improved range analysis in fixed-point polynomial data-path’, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017, 36, pp. 19251929.
    22. 22)
      • 19. De Caro, D., Napoli, E., Esposito, D., et al: ‘Minimizing coefficients wordlength for piecewise-polynomial hardware function evaluation with exact or faithful rounding’, IEEE Trans. Circuits Syst. I Regul. Pap., 2017, 64, pp. 11871200.
    23. 23)
      • 21. Pang, Y., Yan, Y., Lin, J., et al: ‘ICAT: engine to perform range analysis and allocate bit-widths for arithmetic datapaths’, J. Circuits Syst. Comput., 2015, 24, p. 1550020.
    24. 24)
      • 7. Shi, C., Brodersen, R.: ‘Automated fixed-point data-type optimization tool for signal processing and communication systems’. Proc. Des. Autom. Conf, San Diego, CA, USA, 2004, pp. 478483.
    25. 25)
      • 2. Lee, D., Gaffar, A.A., Cheung, R.C.C., et al: ‘Accuracy-guaranteed bit-width optimization’, IEEE Trans. Comput-Aided Design, 2006, 25, pp. 19902000.
    26. 26)
      • 1. Pang, Y., Radecka, K., Zilic, Z.: ‘An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits’. Proc. ASP-DAC, Yokohama, Japan, 2011, pp. 455460.
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