Gate diffusion input based 4-bit Vedic multiplier design

Gate diffusion input based 4-bit Vedic multiplier design

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A multiplier is one of the key hardware blocks in most of the processors. Multiplication is a lengthy, time-consuming task. Vedic multiplication in field programmable gate array implementation has been proven effective in reducing the number of steps and circuit delay. Conventionally at the circuit level, complementary metal oxide semiconductor (CMOS) logic is used to design a multiplier. In CMOS circuits, the area is always an issue. Gate diffusion input (GDI)-based logic has been explored in the literature to reduce the number of transistors for various logic functions. Thus, Vedic mathematics, on the one hand, simplifies the multiplication process and reduces the delay; while on the other hand, GDI technique helps in minimising the transistor count (TC) and reduction in power. Therefore, this study puts forth a GDI logic-based 4-bit Vedic multiplier. To study the effectiveness of the GDI logic, the transient response of a 2-bit Vedic multiplier using CMOS and GDI is compared. For the 4-bit Vedic multiplier, two design approaches are taken into consideration. The performance of these circuits is analysed in terms of average power dissipation, delay, and TC. The effect of supply voltage scaling is also studied. The circuit simulations are carried out at 130 nm for bulk metal oxide semiconductor field effect transistor predictive technology model-based device parameters.


    1. 1)
      • 1. Poornima, M., Patil, S.K., Shivukumar Shridhar, K.P., et al: ‘Implementation of multiplier using Vedic algorithm’, Int. J. Innov. Technol. Exploring Eng., 2013, 2, (6), pp. 219223.
    2. 2)
      • 2. Suma, S., Sridhar, V.: ‘Design of multiplier for medical image compression using Urdhava Tiryakbhyam sutra’, Int. J. Electr. Comput. Eng., 2016, 6, (3), pp. 11401151.
    3. 3)
      • 3. Gaikwad, K.M., Chavan, M.S.: ‘Vedic mathematics for digital signal processing operations: a review’, Int. J. Comput. Applic., 2015, 113, (18), pp. 1014.
    4. 4)
      • 4. Kunchigi, V., Kulkarni, L., Kulkarni, S., et al: ‘Simulation of Vedic multiplier in DCT applications’, Int. J. Comput. Applic., 2013, 63, (16), pp. 2732.
    5. 5)
      • 5. Savadi, A., Yanamshetti, R., Biradar, S.: ‘Design and implementation of 64 bit IIR filter using Vedic multipliers’. Int. Conf. on Computational Modeling and Security, Bengaluru, India, 2016, vol. 85, pp. 790797.
    6. 6)
      • 6. Anjana, S., Pradeep, C., Samuel, P.: ‘Synthesize of high speed floating-point multipliers based on Vedic mathematics’. Int. Conf. on Information and Communication Technologies, Kochi, India, 2015, vol. 46, pp. 12941302.
    7. 7)
      • 7. Sudeep, M.C., SharathBimba, M., Vucha, M.: ‘Design and FPGA implementation of high speed Vedic multiplier’, Int. J. Comput. Applic., 2014, 90, (16), pp. 69.
    8. 8)
      • 8. Panigrahi, S.R., Das, O.P., Tripathy, B.B., et al: ‘FPGA implementation of 4 × 4 Vedic multiplier’, Int. J. Eng. Res. Dev., 2013, 7, (1), pp. 7680.
    9. 9)
      • 9. Morgenshtein, A., Fish, A., Wagner, I.A.: ‘Gate-diffusion input (GDI) – a technique for low power design of digital circuits: analysis and characterization’. IEEE Int. Symp. on Circuits and Systems, Phoenix-Scottsdale, AZ, USA, 2002, pp. 477480.
    10. 10)
      • 10. Foroutan, V., Taheri, M., Navi, K., et al: ‘Design of two low-power full adder cells using GDI structure and hybrid CMOS logic style’, Integr. VLSI J., 2014, 47, (1), pp. 4861.
    11. 11)
      • 11. Saji, J., Kamal, S.: ‘GDI logic implementation of uniform sized CSLA architectures in 45 nm SOI technology’, Microprocess. Microsyst., 2017, 49, pp. 1827.
    12. 12)
      • 12. Morgenshtein, A., Yuzhaninov, V., Kovshilovsky, A., et al: ‘Full-swing gate diffusion input logic - case-study of low-power CLA adder design’, VLSI J., 2014, 47, pp. 6270.
    13. 13)
      • 13. Bhowmick, R., Manjula, J.: ‘Design of PLL based frequency synthesizer using harmonic extraction techniques’, Indian J. Sci. Technol., 2016, 9, (38), pp. 17.
    14. 14)
      • 14. Hiremath, S., Koppad, D.: ‘Low power circuits using modified gate diffusion input (GDI)’, IOSR J. VLSI Signal Process., 2014, 4, (5), pp. 7076.
    15. 15)
      • 15. Patel, R.S., Nagpara, B.H., Pattani, K.M.: ‘Design and implementation of 8 × 8 Vedic multiplier using submicron technology’, Int. J. Mod. Trends Eng. Res., 2016, 3, (2), pp. 536542.
    16. 16)
      • 16. Wang, D., Yang, M., Cheng, W., et al: ‘Novel low power full adder cells in 180 nm CMOS technology’. IEEE Conf. on Industrial Electronics and Applications, Xi'an, China, 2009, pp. 430433.
    17. 17)
      • 17. Abiri, E., Darabi, A.: ‘A novel design of low power and high read stability ternary SRAM (T-SRAM), memory based on the modified gate diffusion input (m-GDI) method in nanotechnology’, Microelectron. J., 2017, 58, pp. 4459.
    18. 18)
      • 18. Shoba, M., Nakkeeran, R.: ‘GDI based full adders for energy efficient arithmetic applications’, Eng. Sci. Technol. Int. J., 2016, 19, (1), pp. 485496.
    19. 19)
      • 19. Cao, Y.: ‘Predictive technology model for robust nanoelectronics design, integrated circuits and systems’ (Springer, Science + Business Media, New York, USA, 2011), pp. 728, Chapter-2, LLC 2011.
    20. 20)
      • 20. Tripathy, S., Omprakash, L.B., Mandal, S.K., et al: ‘Low power multiplier architectures using Vedic mathematics in 45 nm technology for high speed computing’. Int. Conf. on Communication, Information & Computing Technology, Mumbai, India, 2015, pp. 16.
    21. 21)
      • 21. Singh, N., Alam, M.Z.: ‘Design and implementation of 8-Bit multiplier using M.G.D.I technique’, Int. J. Mod. Eng. Res., 2014, 4, (11), pp. 714.
    22. 22)
      • 22. Rudagi, J.M., Ambli, V., Munavalli, V., et al: ‘design and implementation of efficient multiplier using Vedic mathematics’. Int. Conf. on Advances in Recent Technologies in Communication and Computing, Bangalore, India, 2011, pp. 162166.
    23. 23)
      • 23. Pokhriyal, N., Prakash, N.R.: ‘Area efficient low power Vedic multiplier design using GDI technique’, Int. J. Eng. Trends Technol., 2014, 15, (4), pp. 196199.
    24. 24)
      • 24. Shoba, M., Nakkeeran, R.: ‘Energy and area efficient hierarchy multiplier architecture based on Vedic mathematics and GDI logic’, Eng. Sci. Technol. J., 2017, 20, (1), pp. 321331.
    25. 25)
      • 25. Kumar, P., Yadav, P.: ‘Design and analysis of GDI based full adder circuit for low power applications’, Int. J. Eng. Res. Applic., 2014, 4, (3), pp. 462465.

Related content

This is a required field
Please enter a valid email address