Digital LDO modelling techniques for performance estimation at early design stage

Digital LDO modelling techniques for performance estimation at early design stage

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This work studies the transient responses and steady-state ripples of digital low dropout (LDO) voltage regulators. Simulation models as well as closed-form expressions are provided for estimating the LDO output settling behaviour after load current or reference voltage changes. Estimation equations for the magnitude and frequency of LDO output steady-state ripples are also presented. The accuracy of the developed models is verified by comparing estimation data with results obtained from circuit simulations. The use of the developed estimation equations in design space exploration is also demonstrated.


    1. 1)
      • 1. Kim, S.T., Shih, Y.-C., Mazumdar, K., et al: ‘Enabling wide autonomous DVFS in a 22 nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation’. Proc. Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, February 2015, pp. 154155.
    2. 2)
      • 2. Luria, K., Shor, J., Zelikson, M., et al: ‘Dual-use low-drop-out regulator/power gate with linear and on-off conduction modes for microprocessor on-die supply voltages in 14nm’. Proc. Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, February 2015, pp. 156157.
    3. 3)
      • 3. Okama, Y., Ishida, K., Ryu, Y., et al: ‘0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65 nm CMOS’. Proc. Custom Integrated Circuits Conf. (CICC), San Jose, 2010.
    4. 4)
      • 4. Lee, Y.-H., Peng, S.-Y., Wu, A.C.-H., et al: ‘A 50 nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40 nm CMOS for 5.6 times MIPS performance’. Proc. Symp. VLSI Circuits, Honolulu, HI, 2012, pp. 178179.
    5. 5)
      • 5. Oh, T.J., Hwang, I.C.: ‘A 110-nm CMOS 0.7-V input transient-enhanced digital low-dropout regulator with 99.98% current efficiency at 80-mA load’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2015, 23, (7), pp. 12811286.
    6. 6)
      • 6. Raychowdhury, A., Somasekhar, D., Tschanz, J., et al: ‘A fully-digital phase-locked low dropout regulator in 32 nm CMOS’. Proc. 2012 Symp. VLSI Circuits, Honolulu, HI, 2012, pp. 148149.
    7. 7)
      • 7. Yang, F., Mok, P.K.T.: ‘A 0.6–1 V input capacitor-less asynchronous digital LDO with fast transient response achieving 9.5b over 500 mA loading range in 65-nm CMOS’. Proc. European Solid-State Circuits Conf. (ESSCIRC), Graz, 2015, pp. 180183.
    8. 8)
      • 8. Tai, C.L., Roth, A., Soenen, E.: ‘A digital low drop-out regulator with wide operating range in a 16 nm FinFET CMOS process’. Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Xiamen, 2015.
    9. 9)
      • 9. Kim, Y., Li, P.: ‘A 0.38 V near/sub-VT digitally controlled low-dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process’, IET Circuits Dev. Syst., 2013, 7, (1), pp. 3141.
    10. 10)
      • 10. Peng, S.Y., Huang, T.-C., Lee, Y.-H., et al: ‘Instruction-cycle-based dynamic voltage scaling power management for low-power digital signal processor with 53% power savings’, IEEE J. Solid-State Circuits, 2013, 48, (11), pp. 26492661.
    11. 11)
      • 11. Nasir, S.B., Gangopadhyay, S., Raychowdhury, A.: ‘A 0.13 μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range’. Proc. Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, February 2015, pp. 9899.
    12. 12)
      • 12. Chiu, C.C., Huang, P.-H., Lin, M., et al: ‘A 0.6 V resistance-locked loop embedded digital low dropout regulator in 40 nm CMOS with 77% power supply rejection improvement’. Symp. VLSI Circuits Digest Technical Papers, June 2013, pp. 166167.
    13. 13)
      • 13. Gangopadhyay, S., Somasekhar, D., Tschanz, J.W., et al: ‘A 32 nm embedded, fully-digital, phase-locked low dropout regulator for fine grained power management in digital circuits’, IEEE J. Solid-State Circuits, 2014, 49, (11), pp. 26842693.
    14. 14)
      • 14. Yang, F., Mok, P.K.T.: ‘Fast-transient asynchronous digital LDO with load regulation enhancement by soft multi-step switching and adaptive timing techniques in 65-nm CMOS’. 2015 IEEE Custom Integrated Circuits Conf. (CICC), San Jose, CA, 2015, pp. 14.
    15. 15)
      • 15. Song, H., Rhee, W., Shim, I., et al: ‘Digital LDO with 1-bit ΔΣ modulation for low-voltage clock generation systems’, Electron. Lett., 2016, 52, (25), pp. 20342036.
    16. 16)
      • 16. Kim, D., Seok, M.: ‘8.2 fully integrated low-drop-out regulator based on event-driven PI control’. IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, 2016, pp. 148149.
    17. 17)
      • 17. Lee, Y.J., Qu, W., Singh, S., et al: ‘A 200-mA digital low drop-out regulator with coarse-fine dual loop in mobile application processor’, IEEE J. Solid-State Circuits, 2017, 52, (1), pp. 6476.
    18. 18)
      • 18. Lee, B.: ‘Technical review of low dropout voltage regulator operation and performance’, Texas Instruments Application Note, 1999.
    19. 19)
      • 19. Simrock, S.: ‘Control theory’. Proc. CERN Accelerator School on Digital Signal Processing, 2007, pp. 73130.
    20. 20)
      • 20. Leitner, S., West, P., Lu, C., et al: ‘Digital LDO modeling for early design space exploration’. Proc. 29th IEEE Int. System on Chip Conf., Seattle, WA, 6–9 September 2016, pp. 712.
    21. 21)
      • 21. Giustolisi, G., Palumbo, G., Spitale, E.: ‘Robust miller compensation with current amplifiers applied to LDO voltage regulators’, IEEE Trans. Circuits Syst. I, 2012, 59, (9), pp. 18801893.
    22. 22)
      • 22. Ho, E.N.Y., Mok, P.K.T.: ‘A capacitor-less CMOS active feedback low-dropout regulator with slew-rate enhancement for portable on-chip application’, IEEE Trans. Circuits Syst. II Express Briefs, 2010, 57, (2), pp. 8084.
    23. 23)
      • 23. Wu, J., Boyer, A., Li, J., et al: ‘Modeling and simulation of LDO voltage regulator susceptibility to conducted EMI’, IEEE Trans. Electromagn. Compat., 2014, 56, (3), pp. 726735.
    24. 24)
      • 24. Pérez-Bailón, J., Márquez, A., Calvo, B., et al: ‘Fast-transient high-performance 0.18 μm CMOS LDO for battery-powered systems’, Electron. Lett., 2017, 53, (8), pp. 551552.
    25. 25)
      • 25. Kim, D., Seok, M.: ‘A fully integrated digital low-dropout regulator based on event-driven explicit time-coding architecture’, IEEE J. Solid-State Circuits, 2017, 53, (11), pp. 30713080.

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