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Elastic buffer evaluation for link pipelining under process variation

Elastic buffer evaluation for link pipelining under process variation

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Network-on-chip (NoC) adopted for many-core intercommunications may face long link delay and power consumption limitations. A proven solution is to segment long links with storage elements or repeaters. Besides, a new design paradigm called elastic has been considered in the literature, which seems suitable for NoC designs. In this study, the authors explore the benefit of various elastic-buffer (EB) structures to be used for link pipelining. They study elastic handshaking protocols and explore various elastic buffer designed to be used in NoC era. They propose to use synchronous elastic flow (SELF) handshaking protocol for link pipelining. Results show elastic buffer structure based on SELF-handshaking protocol, which can run at least with 21% higher frequency, has 25% less delay and consumes 8% less power compared with other proposed designs. They have explored the process variation issues with various scenarios on seven different structures. They have improved the SELF-elastic buffer, which is more resilient against process variation, proposing two new structures. The new proposed structures exhibit about 5% better performance and 13% less power delay product variation in average.


    1. 1)
      • 14. Mamaghani, M.J., Krstic, M., Garside, J.: ‘Automatic clock: a promising approach toward GALSification’. 2016 22nd IEEE Int. Symp. Asynchronous Circuits and Systems (ASYNC), 2016, pp. 8384.
    2. 2)
      • 21. Ezz-Eldin, R., El-Moursy, M.A., Hamed, H.F.A.: ‘Analysis and design of networks-on-chip under high process variation’ (Springer International Publishing, Cham, 2015).
    3. 3)
      • 12. Bohnenstiehl, B., Stillmaker, A., Pimentel, J.J., et al: ‘Kilocore: a 32 nm 1000-processor computational array’, IEEE J. Solid-State Circuits, 2017, 52, (4), pp. 891902.
    4. 4)
      • 29. Michelogiannakis, G.: ‘Energy-efficient flow control for on-chip networksPhD thesis, (Stanford University, 2012).
    5. 5)
      • 35. Kauppila, A.V.: ‘Analysis of parameter variation impact on the single event response in sub-100 nm CMOS storage cells’, Vanderbilt, 2012.
    6. 6)
      • 33. Robert, C.P., Casella, G.: ‘Monte Carlo statistical methods’ (Springer New York, New York, NY, 2004).
    7. 7)
      • 8. Carloni, L.P., McMillan, K.L., Sangiovanni-Vincentelli, A.L.: ‘Theory of latency-insensitive design’, IEEE Trans. Comput. Des. Integr. Circuits Syst., 2001, 20, (9), pp. 10591076.
    8. 8)
      • 18. Nazir, L., Naaz Mir, R.: ‘Realization of efficient high throughput buffering policies for network on chip router’, Int. J. Comput. Netw. Inf. Secur., 2016, 8, (7), pp. 6170.
    9. 9)
      • 24. Jose, A.P., Patounakis, G., Shepard, K.L.: ‘Pulsed current-mode signaling for nearly speed-of-light intrachip communication’, IEEE J. Solid-State Circuits, 2006, 41, (4), pp. 772780.
    10. 10)
      • 22. Blaauw, D., Chopra, K., Srivastava, A., et al: ‘Statistical timing analysis: from basic principles to state of the art’, IEEE Trans. Comput. Des. Integr. Circuits Syst., 2008, 27, (4), pp. 589607.
    11. 11)
      • 17. Michelogiannakis, G., Becker, D., Dally, W.: ‘Evaluating elastic buffer and wormhole flow control’, IEEE Trans. Comput., 2011, 60, (6), pp. 896903.
    12. 12)
      • 26. Mark Jones, A.: ‘Asynchronous communication among hardware object nodes in IC with receive and send ports protocol registers using temporary register bypass select for validity information’, 2008.
    13. 13)
      • 19. Stefano, B., Bertozzi, D., Benini, L., et al: ‘Process variation tolerant pipeline design through a placement-aware multiple voltage island design style’. 2008 Design, Automation and Test, Europe, Munich, Germany, 2008, pp. 967972.
    14. 14)
      • 3. Yasudo, R., Matsutani, H., Koibuchi, M., et al: ‘Scalable networks-on-chip with elastic links demarcated by decentralized routers’, IEEE Trans. Comput., 2016, PP, (99), pp. 702716.
    15. 15)
      • 6. Kodi, A.K., Sarathy, A., Louri, A.: ‘Adaptive channel buffers in on-chip interconnection networks – a power and performance analysis’, IEEE Trans. Comput., 2008, 57, (9), pp. 11691181.
    16. 16)
      • 11. You, J., Xu, Y., Han, H., et al: ‘Performance evaluation of elastic GALS interfaces and network fabric’, Electron. Notes Theor. Comput. Sci., 2008, 200, (1), pp. 1732.
    17. 17)
      • 36. Mirzaei, M., Mosaffa, M., Mohammadi, S.: ‘Variation-aware approaches with power improvement in digital circuits’, Integr. VLSI J., 2015, 48, (1), pp. 83100.
    18. 18)
      • 20. Cortadella, J., Kishinevsky, M., Grundmann, B.: ‘SELF: specification and design of a synchronous elastic architecture for DSM systems’. Int. Workshop Timing Issues Specification Synthesis Digital Systems, Tel-Aviv University Academic & Science, 2006.
    19. 19)
      • 2. Ditomaso, D., Morris, R., Kodi, A.K., et al: ‘Extending the energy efficiency and performance with channel buffers, crossbars, and topology analysis for network-on-chips’, IEEE Trans. Very Large Scale Integr. Syst., 2013, 21, (11), pp. 21412154.
    20. 20)
      • 7. Michelogiannakis, G., Dally, W.J.: ‘Elastic buffer flow control for on-chip networks’, IEEE Trans. Comput., 2013, 62, (2), pp. 295309.
    21. 21)
      • 32. Dimitrakopoulos, G., Psarras, A., Seitanidis, I.: ‘Microarchitecture of network-on-chip routers’ (Springer New York, New York, NY, 2015).
    22. 22)
      • 5. Aldammas, A., Soudani, A., Al-dhelaan, A.: ‘The efficiency of buffer and buffer-less data-flow control schemes for congestion avoidance in networks on chip’, J. King Saud Univ. Comput. Inf. Sci., 2016, 28, (2), pp. 184198.
    23. 23)
      • 28. Krstic, S., Cortadella, J., Kishinevsky, M., et al: ‘Synchronous elastic networks’. 2006 Formal Methods in Computer Aided Design, San Jose, CA, USA, 2006, vol. 2, pp. 1930.
    24. 24)
      • 15. Psarras, A., Moisidis, S., Nicopoulos, C., et al: ‘Networks-on-chip with double-data-rate links’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2017, 64, (12), pp. 31033114.
    25. 25)
      • 9. Carmona, J., Cortadella, J., Kishinevsky, M., et al: ‘Elastic circuits’, IEEE Trans. Comput. Des. Integr. Circuits Syst., 2009, 28, (10), pp. 14371455.
    26. 26)
      • 27. Miro Panades, I., Greiner, A.: ‘Bi-synchronous FIFO for synchronous circuit communication well suited for network-on-chip in GALS architectures’. First Int. Symp.n Networks-on-Chip (NOCS'07), Princeton, NJ, USA, 2007, pp. 8394.
    27. 27)
      • 4. Seitanidis, I., Psarras, A., Dimitrakopoulos, G., et al: ‘Elastistore: an elastic buffer architecture for network-on-chip routers’. Design, Automation and Test in Europe Conf. Exhibition, Dresden, Germany, 2014, vol. 1, pp. 16.
    28. 28)
      • 16. Hassan, S.M., Yalamanchili, S.: ‘Centralized buffer router: a low latency, low power router for high radix NOCs’. 2013 Seventh IEEE/ACM Int. Symp. Networks-on-Chip (NoCS), Tempe, AZ, USA, 2013, pp. 18.
    29. 29)
      • 23. Hernandez, C., Silla, F., Duato, J.: ‘A methodology for the characterization of process variation in NoC links’. 2010 Design, Automation & Test in Europe Conf. Exhibition, Dresden, Germany, 2010, pp. 685690.
    30. 30)
      • 30. Gebhardt, D., Stevens, K.S.: ‘Elastic flow in an application specific network-on-chip’, Electron. Notes Theor. Comput. Sci., 2008, 200, (1), pp. 315.
    31. 31)
      • 34. Alioto, M., Member, S., Palumbo, G., et al: ‘Understanding the effect of process variations on the delay of static and domino logic’, IEEE Trans. Very Large Scale Integr. Syst., 2010, 18, (5), pp. 697710.
    32. 32)
      • 10. Seitanidis, I., Psarras, A., Kalligeros, E., et al: ‘Elastinoc: a self-testable distributed VC-based network-on-chip architecture’. 2014 Eighth IEEE/ACM Int. Symp. Networks-on-Chip (NoCS), Ferrara, Italy, 2014, pp. 135142.
    33. 33)
      • 1. Banerjee, K., Mehrotra, A.: ‘A power-optimal repeater insertion methodology for global interconnects in nanometer designs’, IEEE Trans. Electron Devices, 2002, 49, (11), pp. 20012007.
    34. 34)
      • 13. Schoeberl, M., Sparso, J.: ‘Timing organization of a real-time multicore processor’. 2017 New Generation of CAS (NGCAS), Genova, Genoa, 2017, pp. 8992.
    35. 35)
      • 31. Casu, M.R.: ‘Improving synchronous elastic circuits: token cages and half-buffer retiming’. 2010 IEEE Symp. Asynchronous Circuits and Systems, Grenoble, France, 2010, pp. 128137.
    36. 36)
      • 25. Mondal, M., Ragheb, T., Wu, X., et al: ‘Provisioning on-chip networks under buffered RC interconnect delay variations’. Eighth Int. Symp. Quality Electronic Design (ISQED'07), San Jose, CA, USA, 2007, pp. 873878.

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