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access icon free Low-power successive approximation ADC using split-monotonic capacitive DAC

© The Institution of Engineering and Technology
Received 24/08/2017, Accepted 20/10/2017, Revised 03/10/2017, Published 27/10/2017

A power-efficient successive approximation analogue-to-digital converter (SA-ADC) is proposed. In order to reduce the energy consumption of the employed capacitive digital-to-analogue converter (DAC), a new low-energy capacitor switching technique is proposed which consumes no switching energy during the first three comparison steps. Moreover, an energy-efficient split-monotonic technique is utilised for the rest of the operations. Compared with the capacitor switching technique used in the conventional SA-ADC, the proposed scheme not only reduces the switching energy by 99.23% but also it has lowered the total capacitor size by 75%. Furthermore, in order to realise the proposed capacitor switching scheme, a power-efficient logic circuit is designed which reduces the power consumption of the required control logic circuit by reducing the activity of the employed D-type flip-flops. Based on the proposed scheme, a 10 bit 40 kS/s SA-ADC has been designed and simulated in a 0.18 µm complementary metal-oxide semiconductor technology with a supply voltage of 1 V. Post-layout simulation results show that the proposed ADC circuit achieves a signal-to-noise-and-distortion ratio of 60.8 dB at the cost of 270 nW power consumption, resulting in a figure-of-merit of 7.6 fJ/conversion step.

Inspec keywords: logic design; integrated circuit layout; digital-analogue conversion; CMOS logic circuits; analogue-digital conversion; capacitor switching; flip-flops; low-power electronics

Other keywords: D-type flip-flop; low power-efficient successive approximation analogue-to-digital converter; power 270 nW; power consumption; signal-to-noise-and-distortion ratio; noise figure 60.8 dB; DAC; CMOS technology; post-layout simulation; control logic circuit; voltage 1 V; word length 10 bit; SA-ADC; power efficient logic circuit design; energy efficient split-monotonic capacitive digital-to-analogue converter; low-energy capacitor switching technique; size 0.18 mum; energy consumption

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; A/D and D/A convertors; Digital circuit design, modelling and testing; Logic and switching circuits; Logic circuits; A/D and D/A convertors; CMOS integrated circuits; Logic design methods

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