access icon free Soft input decoder for high-rate generalised concatenated codes

Generalised concatenated (GC) codes are well suited for error correction in flash memories for high-reliability data storage. The GC codes are constructed from inner extended binary Bose–Chaudhuri–Hocquenghem (BCH) codes and outer Reed–Solomon codes. The extended BCH codes enable high-rate GC codes and low-complexity soft input decoding. This work proposes a decoder architecture for high-rate GC codes. For such codes, outer error and erasure decoding are mandatory. A pipelined decoder architecture is proposed that achieves a high data throughput with hard input decoding. In addition, a low-complexity soft input decoder is proposed. This soft decoding approach combines a bit-flipping strategy with algebraic decoding. The decoder components for the hard input decoding can be utilised which reduces the overhead for the soft input decoding. Nevertheless, the soft input decoding achieves a significant coding gain compared with hard input decoding.

Inspec keywords: binary codes; concatenated codes; BCH codes; computational complexity; integrated circuit reliability; error correction codes; Reed-Solomon codes; decoding; flash memories

Other keywords: extended BCH codes; soft input decoder; low-complexity soft input decoder; high-rate generalised concatenated codes; flash memories; coding gain; error correction; soft decoding approach; decoder architecture; high-reliability data storage; high-rate GC codes; bit-flipping strategy; hard input decoding; outer Reed-Solomon codes; erasure decoding; algebraic decoding; pipelined decoder architecture; low-complexity soft input decoding; inner extended binary Bose-Chaudhuri-Hocquenghem codes; outer error

Subjects: Semiconductor storage; Reliability; Codes; Codecs, coders and decoders; Memory circuits

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