Design techniques of all-digital arithmetic units for time-mode signal processing

Design techniques of all-digital arithmetic units for time-mode signal processing

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

This study provides a comprehensive treatment of the design techniques of all-digital arithmetic units for time-mode signal processing. The arithmetic units investigated include time polarity detectors, time absolute-value generators, time adders, time baluns, time amplifiers, time quantisers, time registers, and time integrators. The principle, circuit implementation, constraints and limitations of these units are investigated in detail. An emphasis is given to time adders and time integrators. An in-depth study of time adders constructed from switched delay units, dual discharge paths, and unidirectional gated delay lines is provided. It is followed with the presentation of three time registered evolved from these time adders. Three time integrators developed from the preceding time adders and time registers are studied and their characteristics are compared. Finally, the design of a first-order time-to-digital converter utilising these arithmetic units is presented.


    1. 1)
      • 1. Li, G., Tousi, Y., Hassibi, A., et al: ‘Delay-line-based analog-to-digital converters’, IEEE Trans. Circuits Syst. II, 2009, 56, (6), pp. 464468.
    2. 2)
      • 2. Straayer, M., Perrott, M.: ‘A 12-bit, 10-MHz bandwidth, continuous-time ▵Ʃ ADC with a 5-bit, 950-MS/s VCO-based quantizer’, IEEE J. Solid-State Circuits, 2008, 43, (4), pp. 805814.
    3. 3)
      • 3. Park, M., Perrott, M.: ‘A single-slope 80 Ms/s ADC using two-step time-to-digital conversion’. IEEE Int. Symp. Circuits System, 2009, pp. 11251128.
    4. 4)
      • 4. Jang, T., Kim, J., Yoon, Y., et al: ‘A highly-digital VCO-based analog-to-digital converter using phase interpolator and digital calibration’, IEEE Trans. VLSI Syst., 2012, 20, (8), pp. 13681372.
    5. 5)
      • 5. Yu, W., Kim, J., Kim, K., et al: ‘A time-domain high-order MASH ▵Ʃ ADC using voltage-controlled gated-ring oscillator’, IEEE Trans. Circuits Syst. I., 2013, 60, (4), pp. 856866.
    6. 6)
      • 6. Yu, W., Kim, K., Cho, S.: ‘A 148 fsrms integrated noise 4 MHz bandwidth second-order ▵Ʃ time-to-digital converter with gated switched-ring oscillator’, IEEE Trans. Circuits Syst. I, 2014, 61, (8), pp. 22812289.
    7. 7)
      • 7. Kim, J., Kim, Y., Kim, K., et al: ‘A hybrid-domain two-step time-to- digital converter using a switch-based time-to-voltage converter and SAR ADC’, IEEE Trans. Circuits Syst. II, 2017, 62, pp. 631635.
    8. 8)
      • 8. Tokairin, T., Okada, M., Kitsunezuka, M., et al: ‘A 2.1-to-2.8-GHz low-phase-noise all-digital frequency synthesizer with a time-windowed time-to-digital converter’, IEEE J. Solid-State Circuits, 2010, 45, (12), pp. 25822590.
    9. 9)
      • 9. Hong, J., Kim, S., Liu, J., et al: ‘A 0.004 mm2 250 μW▵Ʃ TDC with time-difference accumulator and a 0.012 mm2 2.5 mW bang-bang digital PLL using PRNG for low-power SoC applications’. IEEE Int. Conf. Solid-State Circuits Digest Technical Papers, San Francisco, USA, 2012, pp. 240242.
    10. 10)
      • 10. Park, Y., Yuan, F.: ‘Low-power all-digital delta-sigma TDC with bi-directional gated delay line time integrator’. IEEE Mid-West Symp. Circuits and Systems, Boston, MA, USA, 2017, pp. 679682.
    11. 11)
      • 11. Dehlaghi, B., Magierowski, S., Belostotski, L.: ‘Highly-linear time-difference amplifier with low sensitivity to process variations’, IET Electron. Lett., 2011, 47, (13), pp. 743745.
    12. 12)
      • 12. Kwon, H., Lee, J., Sim, J., et al: ‘A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio’. Proc. IEEE Asian Solid-State Circuits Conf., Jeju, South Korea, 2011, pp. 325328.
    13. 13)
      • 13. Lee, M., Abidi, A.: ‘A 9B, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue’, IEEE J. Solid-State Circuits, 2008, 43, (4), pp. 769777.
    14. 14)
      • 14. Kim, K., Kim, Y., Yu, W., et al: ‘A 7b 3.75 ps resolution two-step time-to-digital converter in 65 nm CMOS using pulse-train time amplifier’, IEEE J. Solid-State Circuits, 2013, 48, (4), pp. 10091017.
    15. 15)
      • 15. Taillefer, C., Roberts, G.: ‘Delta-sigma A/D converter via time-mode signal processing’, IEEE Trans. Circuits Syst. I, 2009, 56, (9), pp. 19081920.
    16. 16)
      • 16. Ali-Bakhshian, M., Roberts, G.: ‘Digital storage, addition and subtraction of time-mode variables’, IET Electron. Lett., 2011, 47, (16), pp. 910911.
    17. 17)
      • 17. Kim, K., Yu, W., Cho, S.: ‘A 9 bit, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register’, IEEE J. Solid-State Circuits, 2014, 49, (4), pp. 10071016.
    18. 18)
      • 18. Park, Y., Amor, D., Yuan, F.: ‘Time integrator for mixed-mode signal processing’. Proc. IEEE Int. Symp. Circuits System, Montreal, Canada, 2016, pp. 826829.
    19. 19)
      • 19. Pekau, H., Yousif, A., Haslett, J.: ‘A CMOS integrated linear voltage-to-pulse-delay-time converter for time-based analog-to-digital converters’. Proc. IEEE Int. Symp. Circuits System, Island of Kos, Greece, 2006, pp. 23732376.
    20. 20)
      • 20. Ali-Bakhshian, M., Roberts, G.: ‘A digital implementation of a dual-path time-to-time integrator’, IEEE Trans. Circuits Syst. I, 2012, 59, (11), pp. 25782591.
    21. 21)
      • 21. Park, Y., Yuan, F.: ‘All-digital delta-sigma TDC with differential bi-directional gated-delay-line time integrator’. IEEE Mid-West Symp. Circuits and Systems, Boston, USA, 2017, pp. 15131516.
    22. 22)
      • 22. Chung, S., Hwang, K., Lee, W., et al: ‘A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping’. Proc. IEEE Int. Symp. Circuits System, Paris, France, 2010, pp. 13001303.
    23. 23)
      • 23. Rashidzadeh, R., Ahmadi, M., Miller, W.: ‘An all-digital self-calibration method for a vernier-based time-to-digital converter’, IEEE Trans. Instrum. Meas., 2010, 59, (2), pp. 463469.
    24. 24)
      • 24. Yuan, F.Ed.: ‘CMOS time-mode circuits and systems: fundamentals and applications’ (CRC Press, New York, 2015).
    25. 25)
      • 25. Baird, R., Fiez, T.: ‘Linearity enhancement of multibit Δ_ A/D and D/A converters using data weighted averaging’, IEEE Trans. Circuits Syst. II, 1995, 42, (12), pp. 753762.
    26. 26)
      • 26. Nys, O., Henderson, R.: ‘An analysis of dynamic element matching techniques in sigma-delta modulation’. IEEE Int. Symp. Circuits Syst., Atlanta, USA, 1996, pp. 213234.
    27. 27)
      • 27. Nys, O., Henderson, R.: ‘A 19-bit low-power multibit sigma-delta ADC based on data weighted averaging’, IEEE J. Solid-State Circuits, 1997, 32, (7), pp. 933942.

Related content

This is a required field
Please enter a valid email address