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access icon free Calibration method to reduce the error in logarithmic conversion with its circuit implementation

© The Institution of Engineering and Technology
Received 02/08/2017, Accepted 25/12/2017, Revised 21/11/2017, Published 05/01/2018

Here, based on Mitchell's logarithmic conversion, the authors propose a fast calibration method using a fixed binary code with case judgement, which suppresses the conversion error. The authors developed a highly paralleled circuit serving the proposed calibration method. Differential cascade voltage switch logic (DCVSL) is used to work in both high-speed logic and adiabatic logic and trade-off between power dissipation and operation speed. In addition, a low-cost adiabatic clock generator without any passive component is presented to support a four-phase sine clock for the adiabatic logic operation. An 8-bit logarithmic converter is designed in TSMC 180 nm CMOS. Post-simulation results show that the proposed calibration can reduce the conversion error to 1.55% based on Mitchell's algorithm, the power dissipation varies between 1.12 and 3.709 mW, and the delay is 1.82 ns under operational DCVLS.

Inspec keywords: CMOS logic circuits; clocks; calibration; binary codes

Other keywords: four-phase sine clock; time 1.82 ns; fast calibration method; power dissipation; passive component; highly paralleled circuit; Mitchell's logarithmic conversion; high-speed logic; calibration method; CMOS; logarithmic converter; fixed binary code; size 180 nm; differential cascade voltage switch logic; power 3.709 mW; power 1.12 mW; adiabatic logic; circuit implementation; conversion error; low-cost adiabatic clock generator; word length 8 bit

Subjects: Logic circuits; Logic and switching circuits; CMOS integrated circuits

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