Through-silicon vias (TSVs) are a key technology for three-dimensional integrated circuits. As the integration of circuits increases, high temperature has a greater effect on the performance of the TSV interconnections. The metal–oxide semiconductor (MOS) effect is one of the most important temperature-dependent characteristics of a TSV. This study introduces the mathematical model of a TSV to predict the MOS effect more accurately. The thermal effect that varies due to the change in the TSV capacitance and depletion region can be modelled by the non-linear the Poisson equation including mobile charge carriers. In procedures to solve this equation, the proposed method considers not only the thermal effect of intrinsic carrier concentration and silicon bandgap energy but also the shift effect of the flat band voltage due to the Si–SiO₂ interface charges. In addition, since it considers the minority carrier generation rate, which is dependent on the change of gate voltage, the MOS effect in a TSV can be explained more accurately using equations derived from these procedures. To verify the proposed mathematical model, comparison with the numerical method is carried out, and these results show that the proposed method is very accurate in explaining the MOS effect in a TSV.

References

1. 1)
  - 16. Katti, G., Stucchi, M., De Meyer, K., et al: ‘Electrical modeling and characterization of through silicon via for 3-D ICs’, IEEE Trans. Electron Devices, 2010, 57, (1), pp. 256–262.
2. 2)
  - 7. Cheng, T.-Y., Wang, C.-D., Chiou, Y.-P., et al: ‘A new macro-πmodel for through-silicon vias on 3-D IC using conformal mapping method’, IEEE Trans. Microw. Compon. Lett., 2012, 22, (6), pp. 303–305.
3. 3)
  - 4. Han, K.J., Swaminathan, M., Bandyopadhyay, T.: ‘Electromagnetics modeling of through-silicon via (TSV) interconnections using cylindrical modal basis functions’, IEEE Trans. Adv. Packag., 2010, 33, (4), pp. 804–817.
4. 4)
  - 20. Du, X.Z., Frye, C.D., Edgar, J.H., et al: ‘Temperature dependence of the energy bandgap of two-dimensional hexagonal boron nitride probed by excitonic photoluminescence’, J. Appl. Phys., 2014, 115, p. 053503.
5. 5)
  - 22. Arora, N.: ‘MOSFET models for VLSI circuit simulation’ (Springer-Verlag, New York, 2007), pp. 138–155.
6. 6)
  - 6. Hu, S., Wang, L., Xiong, Y.-Z., et al: ‘TSV technology for millimeter-wave and terahertz design and applications’, IEEE Trans. Compon., Packag., Manuf. Technol., 2011, 1, (2), pp. 260–267.
7. 7)
  - 1. Lu, J.Q.: ‘3-D hyperintegration and packaging technologies for micronano systems’, Proc. IEEE, 2009, 97, (1), pp. 18–30.
8. 8)
  - 21. Sze, S.M., Ng, K.K.: ‘Physics of semiconductor devices’ (Wiley-Interscience, New Jersey, 2007, 3rd edn.), pp. 85–90.
9. 9)
  - 3. Kim, J., Pak, J.S., Cho, J., et al: ‘Highfrequency scalable electrical model and analysis of a through silicon via (TSV)’, IEEE Trans. Compon., Packag., Manuf. Technol., 2011, 1, (2), pp. 181–195.
10. 10)
  - 9. Todri, A., Kundu, S., Girard, P., et al: ‘A study of tapered 3-D TSVs for power and thermal integrity’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2013, 21, (2), pp. 306–319.
11. 11)
  - 13. Bandyopadhyay, T., Chatterjee, R., Chung, D., et al: ‘Electrical modeling of through silicon and package vias’. Proc. IEEE Int. Conf. 3-D System Integration, San Francisco, CA, September 2009, pp. 28–30.
12. 12)
  - 5. Kim, J., Choi, K., Lee, S., et al: ‘6–18 GHz reactive matched GaN MMIC power amplifiers with distributed L-C load matching’, J. Electromagn. Eng. Sci., 2016, 16, (1), pp. 44–51.
13. 13)
  - 2. Liu, C., Song, T., Cho, J., et al: ‘Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC’. Proc. IEEE Design Autom. Conf., New York, NY, USA, January 2011, pp. 783–788.
14. 14)
  - 18. Zhao, W., Zheng, J., Chen, S., et al: ‘Transient analysis of through-silicon vias in floating silicon substrate’, IEEE Trans. Electron Devices, 2017, 59, (1), pp. 207–216.
15. 15)
  - 14. Bandyopadhyay, T., Chatterjee, R., Chung, D., et al: ‘Electrical modeling of annular and co-axial TSVs considering MOS capacitance effects’. Proc. IEEE 18th Conf. Electrical Performance of Electronic Packaging and Systems, Portland, OR, October 2009, pp. 117–120.
16. 16)
  - 12. Fang, R., Sun, X., Miao, M., et al: ‘Characteristics of coupling capacitance between signal-ground TSVs considering MOS effect in silicon interposers’, IEEE Trans. Electron Devices, 2015, 62, (12), pp. 4161–4168.
17. 17)
  - 10. Bandyopadhyay, T., Han, K.J., Chung, D., et al: ‘Rigorous electrical modeling of through silicon vias (TSVs) with MOS capacitance effects’, IEEE Trans. Compon. Packag. Manufac. Technol., 2011, 1, (6), pp. 893–903.
18. 18)
  - 15. Xu, C., Li, H., Suaya, R., et al: ‘Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs’, IEEE Trans. Electron Devices, 2010, 57, (12), pp. 3405–3417.
19. 19)
  - 8. Kim, K., Hwang, K., Ahn, S.: ‘An improved 100 GHz equivalent circuit model of a through silicon via with substrate current loop’, IEEE Microw. Wirel. Compon. Lett., 2016, 26, (6), pp. 425–427.
20. 20)
  - 17. Katti, G., Stucchi, M., Velenis, D., et al: ‘Temperature-dependent modeling and characterization of through-silicon via capacitance’, IEEE Electron Device Lett., 2011, 32, (4), pp. 563–565.
21. 21)
  - 11. Piersanti, S., de Paulis, F., Orlandi, A., et al: ‘Transient analysis of TSV equivalent circuit considering nonlinear MOS capacitance effects’, IEEE Trans. Electromagn. Compat., 2015, 57, (5), pp. 1216–1225.
22. 22)
  - 19. Sproul, A., Green, M.A.: ‘Improved value for the silicon intrinsic carrier concentration from 275 to 375 K’, J. Appl. Phys., 1991, 70, p. 846.

Rigorous mathematical model of through-silicon via capacitance

References

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