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Charge sharing write driver and half- pre-charge 8T SRAM with virtual ground for low-power write and read operation

Charge sharing write driver and half- pre-charge 8T SRAM with virtual ground for low-power write and read operation

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A novel write bitline (BL) charge sharing write driver (CSWD) and a half- read BL (RBL) pre-charge scheme is presented for a single-ended 8T static random access memory (SRAM). Before write enable (WE) signal assertion, CSWD equalises the write BLs by allowing their charge sharing. Both write BLs are equalised at the middle value of supply voltage using leakage current compensation block. Afterwards, as WE signal is asserted, CSWD produces the rail-to-rail levels at write BL pair. Charging of a BL from half- to essentially reduces the write dynamic power dissipation by 50%. Half- pre-charging is used for RBL to achieve low-power read operation. Read port is powered by virtual ground rail to improve the RBL leakages. The authors compare the proposed 8T design (P8T) with conventional 6T (C6T) and 8T (C8T) designs in a 45 nm technology node. Write power dissipation is reduced by 42% and dynamic read power is reduced by more than 39%. Overall leakages are reduced by more than 18% compared with C6T and ratio of the RBL is improved by more than two orders of magnitude compared with conventional 8T (C8T).


    1. 1)
      • 19. Song, T., Kim, S., Lim, K., et al: ‘Fully-gated ground 10T-SRAM bitcell in 45 nm SOI technology’, Electron. Lett., 2010, 46, (7), pp. 515516.
    2. 2)
      • 15. Kanda, K., Miyazaki, T., Sik, M.K., et al: ‘Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic VDD control (RRDV) scheme’. 15th Annual IEEE Int. ASIC/SOC Conf., 2002, 2002, pp. 381385.
    3. 3)
      • 21. Chang, I.J., Kim, J.J., Park, S.P., et al: ‘A 32 kb 10Tt sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS’, IEEE J. Solid-State Circuits, 2009, 44, (2), pp. 650658.
    4. 4)
      • 12. Noguchi, H., Okumura, S., Iguchi, Y., et al: ‘Which is the best dual-port SRAM in 45-nm process technology? – 8T, 10T single end, and 10T differential’. 2008 IEEE Int. Conf. on Integrated Circuit Design and Technology and Tutorial, 2008, pp. 5558.
    5. 5)
      • 11. Yang, B.D., Kim, L.S.: ‘A low-power SRAM using hierarchical bit line and local sense amplifiers’, IEEE J. Solid-State Circuits, 2005, 40, (6), pp. 13661376.
    6. 6)
      • 6. Sinangil, M.E., Chandrakasan, A.P.: ‘Application-specific SRAM design using output prediction to reduce bit-line switching activity and statistically gated sense amplifiers for up to 1.9× lower energy/access’, IEEE J. Solid-State Circuits, 2014, 49, (1), pp. 107117.
    7. 7)
      • 2. Chang, L., Fried, D.M., Hergenrother, J., et al: ‘Stable SRAM cell design for the 32 nm node and beyond’. 2005 Symp. on VLSI Technology. Digest of Technical Papers, 2005, pp. 128129.
    8. 8)
      • 22. Takeda, K., Hagihara, Y., Aimoto, Y., et al: ‘A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications’, IEEE J. Solid-State Circuits, 2006, 41, (1), pp. 113121.
    9. 9)
      • 3. Pavlov, A., Sachdev, M.: ‘CMOS SRAM circuit design and parametric test in nanoscaled technologies: process-aware SRAM design and test’ (Springer Science & Business Media, 2008), vol. 40.
    10. 10)
      • 10. Yang, B.D.: ‘A low-power SRAM using bit-line charge-recycling for read and write operations’, IEEE J. Solid-State Circuits, 2010, 45, (10), pp. 21732183.
    11. 11)
      • 9. Kim, K., Mahmoodi, H., Roy, K.: ‘A low-power SRAM using bit-line charge recycling’, IEEE J. Solid-State Circuits, 2008, 43, (2), pp. 446459.
    12. 12)
      • 13. Maroof, N., Sohail, M., Shin, H.: ‘Charge-sharing read port with bitline precharging and sensing scheme for low-power SRAMs’, Int. J. Circuit Theory Appl., 2016, 45, (9), pp. 12311248. Available at
    13. 13)
      • 8. Kanda, K., Sadaaki, H., Sakurai, T.: ‘90sense-amplifying memory cell’, IEEE J. Solid-State Circuits, 2004, 39, (6), pp. 927933.
    14. 14)
      • 4. Kim, N.S., Austin, T., Blaauw, D., et al: ‘Leakage current: Moore's law meets static power’, Computer, 2003, 36, (12), pp. 6875.
    15. 15)
      • 14. Maroof, N., Kong, B.S.: ‘10T SRAM using half-vtextDD precharge and row-wise dynamically powered read port for low switching power and ultralow RBL leakage’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2017, 25, (4), pp. 11931203.
    16. 16)
      • 16. Wang, B., Nguyen, T.Q., Do, A.T., et al: ‘Design of an ultra-low voltage 9T SRAM with equalized bitline leakage and cam-assisted energy efficiency improvement’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2015, 62, (2), pp. 441448.
    17. 17)
      • 1. Mudge, T.: ‘Power: a first-class architectural design constraint’, Computer, 2001, 34, (4), pp. 5258.
    18. 18)
      • 7. Chang, Y.J., Lai, F., Yang, C.L.: ‘Zero-aware asymmetric SRAM cell for reducing cache power in writing zero’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2004, 12, (8), pp. 827836.
    19. 19)
      • 5. Jeong, H., Kim, T., Song, T., et al: ‘Trip-point bit-line precharge sensing scheme for single-ended SRAM’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2015, 23, (7), pp. 13701374.
    20. 20)
      • 18. Kim, T.H., Liu, J., Keane, J., et al: ‘A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing’, IEEE J. Solid-State Circuits, 2008, 43, (2), pp. 518529.
    21. 21)
      • 17. Calhoun, B.H., Chandrakasan, A.P.: ‘A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation’, IEEE J. Solid-State Circuits, 2007, 42, (3), pp. 680688.
    22. 22)
      • 20. Lutkemeier, S., Jungeblut, T., Berge, H.K.O., et al: ‘A 65 nm 32 b subthreshold processor with 9T multi-VT SRAM and adaptive supply voltage control’, IEEE J. Solid-State Circuits, 2013, 48, (1), pp. 819.

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