access icon free Real-time unified architecture for forward/inverse discrete cosine transform in high efficiency video coding

© The Institution of Engineering and Technology
Received 21/10/2016, Accepted 01/12/2016, Published 12/12/2016

In High Efficiency Video Coding (HEVC) standard, higher video resolutions employ larger integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the authors propose two high-throughput unified DCT/IDCT architectures. The proposed architectures can process variable DCT/IDCT block sizes according to the HEVC standard. The proposed architectures were prototyped on TSMC 65 nm CMOS technology. The prototyping results show that the two unified architectures have throughput of 15.24 and 16.03 Gsps, respectively, and they can encode video sequences with resolutions up to 8 K at 120 fps and decode the same resolution at 240 fps using only one circuit for both DCT and IDCT.

Inspec keywords: discrete cosine transforms; codecs; CMOS integrated circuits; video coding; inverse transforms

Other keywords: size 65 nm; CMOS; high efficiency video coding encoder; HEVC; inverse discrete cosine transform; real-time processing; DCT; video sequences

Subjects: Codecs, coders and decoders; Integral transforms; CMOS integrated circuits; Video signal processing; Image and video coding; Integral transforms

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