access icon free Low-jitter DLL applied for two-segment TDC

© The Institution of Engineering and Technology
Received 07/09/2016, Accepted 06/02/2017, Revised 28/12/2016, Published 20/02/2017

A low-jitter delay-locked loop (DLL) for high-resolution time-to-digital converter (TDC) is proposed in this study. The generated high accurate and low-jitter outputs with uniformly distributed multiphase clocks directly from the voltage-controlled delay line (VCDL) in DLL are applied to two-segment TDC. For reducing the static phase offset in locked state, the charge pump with interior feedback loop is used to achieve a better current matching between the charging and discharging currents. An improved phase detector as well as a differential VCDL excellent in linearity property and noise suppression is utilised for reducing the output clock jitter. Fabricated by TSMC 0.35 μm complementary metal–oxide–semiconductor process, the measurement results show that DLL's frequency locking range is 60–240 MHz, the output clock jitters at 125 MHz are 3.6 ps for root mean square and 35.07 ps for peak-to-peak. By clock period counting and eight-phase discrimination, the resolution of <1 ns and maximum range of around 1 μs as well as the differential non-linearity <0.68 LSB and the integration non-linearity within −0.97 to 1.24 LSB are obtained for two-segment TDC.

Inspec keywords: clocks; timing jitter; charge pump circuits; delay lines; time-digital conversion; mean square error methods; CMOS integrated circuits; delay lock loops

Other keywords: voltage-controlled delay line; low-jitter DLL; time 3.6 ps; interior feedback loop; clock jitter; high-resolution time-to-digital converter; delay-locked loop; TSMC complementary metal–oxide–semiconductor process; frequency 60 MHz to 240 MHz; VCDL; time 35.07 ps; clock period counting; locked state; noise suppression; size 0.35 mum; low-jitter outputs; uniformly distributed multiphase clocks; phase detector; eight-phase discrimination; current matching; static phase offset; linearity property; discharging currents; two-segment TDC; root mean square; charge pump

Subjects: Other digital circuits; Pulse circuits; Other analogue circuits; Interpolation and function approximation (numerical analysis); Interpolation and function approximation (numerical analysis); Power electronics, supply and supervisory circuits; A/D and D/A convertors; A/D and D/A convertors; CMOS integrated circuits

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