access icon free Low-power and high-speed 13T SRAM cell using FinFETs

Fin field-effect transistors (FinFETs) are replacing the traditional planar metal–oxide–semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.

Inspec keywords: SRAM chips; MOSFET; low-power electronics; integrated circuit design

Other keywords: power reduction; leakage current; planar complementary MOS technology; intrinsic body; power dissipation; parameter fluctuations; propagation delay; dopant ions; ST11T cell; sleep transistors approach; power gating technique; low-power static-random access memory cell; gate scalability; gate controllability; short channel effects; fin field-effect transistors; enhancement methods; device-performance variability mitigation; high-speed 13T SRAM cell; speed improvement; performance analysis; FinFET transistor structure; transmission gates; access path

Subjects: Memory circuits; Insulated gate field effect transistors; Semiconductor storage; Digital circuit design, modelling and testing

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