access icon free VLSI Architecture of Full-Search Variable-Block-Size Motion Estimation for HEVC Video Encoding

© The Institution of Engineering and Technology
Received 14/07/2016, Accepted 20/02/2017, Revised 12/02/2017, Published 24/04/2017

Motion estimation (ME) is the most computationally intensive task in video encoding. This study proposes a full-search variable-block-size ME for the high-efficiency video coding or H.265 specification. The proposed method reduces memory requirements to a large extent by following a Morton order for data reading and a sum of absolute differences reuse strategy. The data bandwidth demand is also diminished by broadcasting data into multiple processing elements. This ME accelerator supports variable-block-size prediction blocks ranging from to , and is reconfigurable in various search ranges for a trade-off between performance and area. The proposed method for very-large-scale integration (VLSI) architecture is synthesized with 32 nm technology, and is capable of real-time encoding of ultra-high-definition (4K-UHD, at 30 Hz) video with a search range of 64 pixels in both horizontal and vertical directions, operating at a frequency of 282 MHz.

Inspec keywords: video coding; motion estimation; VLSI; real-time systems

Other keywords: horizontal directions; absolute differences reuse strategy; real-time ultra-high-definition; frequency 282 MHz; multiple processing elements; 4K-UHD; full-search variable-block-size ME; data reading; Morton order; high-efficiency video coding video encoding; motion estimation accelerator; vertical directions; H.265 specification; very large-scale integration architecture; data bandwidth demand; VLSI; data broadcasting; VHDL

Subjects: Video signal processing; Computer vision and image processing techniques; Image and video coding; Semiconductor integrated circuits

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