© The Institution of Engineering and Technology
M-PSK (phase shift keying) modulation schemes are used in many high-speed applications like satellite communication, as they are more bandwidth and power efficient compared with other schemes. This study presents very large scale integrated circuits (VLSI) architectures for modulators and demodulators of quadrature phase shift keying (QPSK), 8PSK and 16PSK systems, based on the principle of direct digital synthesis. The proposed modulators do not use any multiplier in contrast to the conventional modulators and hence they are relatively fast and area efficient. Based on the coherent detection technique, this study proposes new demodulation algorithms for 8PSK and 16PSK systems which can be implemented both in analogue and digital domains. This study also presents VLSI architectures for all the proposed algorithms. The proposed architectures are described in Verilog and implemented on Xilinx field programmable gate arrays (FPGAs). The simulation results verify their functional validity and implementation results show the suitability of the proposed architectures for satellite communications.
References
-
-
1)
-
12. ‘Xilinx Virtex-6 CLB’, .
-
2)
-
6. Vankka, J., Halonen, K.: ‘Direct digital synthesizers—theory, design and applications’ (Kluwer Academic Publishers, 2001).
-
3)
-
14. ‘Digital Video Broadcasting (DVB) User guidelines for the second generation system for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2)’. .
-
4)
-
17. Haykin, S.: ‘Analog and digital communication systems’ (John Weily & Sons Ltd. Publication, 2011, 4th edn.).
-
5)
-
15. Popescu, S.O., Budura, G., Gontean, A.S.: ‘Review of PSK and QAM – digital modulation techniques on FPGA’. Int. Joint Conf. on Computational Cybernatics and Technical Informatics (ICCC-CONTI), Romania, 2010, pp. 327–332.
-
6)
-
7. Cordesses, L.: ‘Direct digital synthesis: a tool for periodic wave generation (part 1)’, IEEE Signal Process. Mag., 2004, 21, (4), pp. 50–54 (doi: 10.1109/MSP.2004.1311140).
-
7)
-
5. Zhang, J., Zhu, L., Guo, Y., et al: ‘A new method of demodulation for 16APSK/32APSK’. 5th Global Symp. on Millimeter waves, Harbin, China, 27–30 May 2012.
-
8)
-
4. Rieth, D., Heller, C., Ascheid, G.: ‘FPGA implementation of shaped offset QPSK modulator’. IEEE Int. Conf. Digital Signal Processing, 2015, pp. 790–793.
-
9)
-
8. Sotiriadis, P.P., Galanopoulos, K.: ‘Direct all-digital frequency synthesis techniques, spurs suppression, and deterministic jitter correction’, IEEE Trans. Circuits Syst., 2012, 59, pp. 958–968 (doi: 10.1109/TCSI.2012.2191875).
-
10)
-
9. Jyothi Chimakurthy, L.S., Ghosh, M., Dai, F.F., et al: ‘A novel DDS using nonlinear ROM addressing with improved compression ratio and quantization noise’, IEEE Trans. Ultrason. Ferroelect. Freq. Control, 2006, 53, (2), pp. 274–283 (doi: 10.1109/TUFFC.2006.1593365).
-
11)
-
1. Sharma, S., Sunil, K., Pujari, V., et al: ‘FPGA implementation of M-PSK modulators for satellite communication’. Int. Conf. Advances in Recent Technologies in Communication and Computing, Kottayam, India, 16–17 October 2010.
-
12)
-
13. ‘Xilinx User Constraints Guide’, .
-
13)
-
2. Popescu, S.O., Gontean, A.S., Ianchis, D.: ‘Implementation of a QPSK System on FPGA’. IEEE 9th Int. Symp. Intelligent Systems and Informatics, Subotica, Serbia, 8–10 September 2011.
-
14)
-
19. Xin, Z., Jun, Q., Bi-hai, T., et al: ‘Design parallel direct digital frequency synthesizer using interpolation and QLA technology’. 8th Int. Conf. on Signal Processing, 2006.
-
15)
-
18. Meyer-Baese, U.: ‘Digital signal processing with field programmable gate arrays’. .
-
16)
-
11. Horowitz, I., La Rue, G.S.: ‘Parallel phase accumulator architecture for DDFS’. IEEE Workshop on Microelectronics and Electron Devices, 2005, pp. 63–66.
-
17)
-
3. Song, W., Yao, Q.: ‘Design and implement of QPSK modem based on FPGA’. 3rd IEEE Int. Conf. Computer Science and Information Technology (ICCSIT), Chengdu, China, 9–11 July 2010, vol. 9.
-
18)
-
10. Tu, J.-H., Van, L.-D.: ‘Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers’, IEEE Trans. Comput., 2009, 58, (10), pp. 1346–1355 (doi: 10.1109/TC.2009.89).
-
19)
-
20. Popescu, S.O., Gontean, A.S., Budura, G.: ‘Simulation and implementation of a BPSK modulator on FPGA’. Proc. of the 6th IEEE Int. Symp. on Applied Computational Intelligence and Informatics (SACI 2011), Romania, 2011, pp. 459–463.
-
20)
-
16. Taub, H., Schilling, D.L.: ‘Principles of communication system 2nd edition’ (Tata Mcgraw-Hill Publishing, New Delhi, 2004).
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2016.0243
Related content
content/journals/10.1049/iet-cds.2016.0243
pub_keyword,iet_inspecKeyword,pub_concept
6
6