access icon free Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing

Field programmable gate array (FPGA) attributes of logic configurability, bitstream storage, and dynamic signal routing can be realised by leveraging the complementary benefits of emerging devices with complementary metal oxide semiconductor (CMOS)-based devices. A novel carbon/magnet lookup table (CM-LUT) is developed and evaluated by trading off a range of mixed heterogeneous technologies to balance energy, delay, and reliability attributes. Herein, magnetic spintronic devices are employed in the configuration memory to contribute non-volatility and high scalability. Meanwhile, carbon nanotube field-effect transistors (CNFETs) provide desirable conductivity, low delay, and low power consumption. The proposed CM-LUT offers ultra-low power and high-speed operation while maintaining high endurance re-programmability with increased radiation-induced soft-error immunity. The proposed four-input one-output CM-LUT utilises 41 CNFETs and 20 magnetic tunnel junctions for read operations and 35 CNFET to perform write operations. Results indicate that CM-LUT achieves an average four-fold energy reduction, eight-fold faster circuit operation and 9.3% reconfiguration power delay product improvement in comparison with spin-based look-up tables. Finally, additional hybrid technology designs are considered to balance performance with the demands of energy consumption for near-threshold operation.

Inspec keywords: CMOS integrated circuits; field programmable gate arrays; table lookup; radiation hardening (electronics); magnetic tunnelling; carbon nanotube field effect transistors; low-power electronics; magnetoelectronics

Other keywords: heterogeneous energy-sparing reconfigurable logic; carbon magnet lookup table; low power consumption; bitstream storage; spin-based storage; high endurance re-programmability; eight-fold faster circuit operation; carbon nanotube field-effect transistors; CM-LUT; logic configurability; magnetic spintronic devices; high-speed operation; complementary metal oxide semiconductor; CNFET-based multiplexing; radiation-induced soft-error immunity; CMOS-based devices; mixed heterogeneous technologies; FPGA; four-fold energy reduction; reconfiguration power delay product improvement; configuration memory; magnetic tunnel junctions; field programmable gate array; dynamic signal routing

Subjects: Logic and switching circuits; Logic circuits; Radiation effects (semiconductor technology); CMOS integrated circuits; Other field effect devices; Fullerene, nanotube and related devices; Electrical/electronic equipment (energy utilisation)

References

    1. 1)
      • 3. Deng, J., Wong, H.P.: ‘A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: Model of the intrinsic channel region’, IEEE Trans. Electron Dev.on, 2007, 54, pp. 31863194.
    2. 2)
      • 13. Liu, B., Cai, L., Zhu, J., et al: ‘On-chip readout circuit for nanomagnetic logic’, IET Circuits Dev. Syst., 2014, 8, pp. 6572.
    3. 3)
      • 27. Fong, X., Choday, S.H., Georgios, P., et al: ‘Purdue nanoelectronics research laboratory magnetic tunnel junction model’, https://nanohub.org/publications/16/1, 2014.
    4. 4)
      • 14. Zhang, Y., Zhao, W., Lakys, Y., et al: ‘Compact modeling of perpendicular-anisotropy CoFeB/MgO magnetic tunnel junctions’, IEEE Trans. Electron Dev.59.3, 2012, pp. 819826.
    5. 5)
      • 25. Zhao, W., Cao, Y.: ‘New generation of predictive technology model for sub-45 nm early design exploration’, IEEE Trans. Electron Dev., 2006, 53, pp. 28162823.
    6. 6)
      • 24. ASU. Predicative Technology Model’: http://ptm.asu.edu/.
    7. 7)
      • 2. Zhao, W., Deng, E., Klein, J.-O., et al: ‘A radiation hardened hybrid spintronic/CMOS nonvolatile unit using magnetic tunnel junctions’, J. Phys. D Appl. Phys., 2014, 47, pp. 405003.
    8. 8)
      • 23. Zand, R., Roohi, A., Salehi, S., et al: ‘Scalable adaptive spintronic reconfigurable logic using area-matched MTJ design’, IEEE Trans. Circuits Syst. II, 2016, 63, (7), in press, pp. 678682.
    9. 9)
      • 6. Han, K.-S., Jeon, D.-I., Chung, K.-S.: ‘Ultra low power and high speed FPGA design with CNFET’. 2012 Int. Symp. on Communications and Information Technologies (ISCIT), 2012, pp. 828833.
    10. 10)
      • 19. Ouyang, M., Huang, J.-L., Cheung, C.L., et al: ‘Energy gaps in ‘metallic’ single-walled carbon nanotubes’, Science, 2001, 292, pp. 702705.
    11. 11)
      • 15. Slonczewski, J.C.: ‘Current-driven excitation of magnetic multilayers’, J. Magn. Magn. Mater., 1996, 159, (1), pp. L1L7.
    12. 12)
      • 12. Dwivedi, A.K., Islam, A.: ‘Design of magnetic tunnel junction-based tunable spin torque oscillator at nanoscale regime’, IET Circuits Dev. Syst.., 2015, 10, (2), pp. 121129.
    13. 13)
      • 26. Stanford University CNFET Model’: https://nano.stanford.edu/stanford-cnfet-model [Accessed 8 March 2017].
    14. 14)
      • 20. Dresselhaus, M., Dresselhaus, G., Saito, R.: ‘Carbon fibers based on C 60 and their symmetry’, Phys. Rev. B, 1992, 45, p. 6234.
    15. 15)
      • 5. Wen, C.-Y., Li, J., Kim, S., et al: ‘A non-volatile look-up table design using PCM (phase-change memory) cells’. 2011 Symp. on VLSI Circuits (VLSIC), 2011, pp. 302303.
    16. 16)
      • 29. Li, X., Zhu, X., Hao, W.: ‘Fast MTJ switching write circuit for MRAM array’. U.S. Patent Application, 13/193,689, filedJanuary 2013.
    17. 17)
      • 22. Radosavljević, M., Lefebvre, J., Johnson, A.: ‘High-field electrical transport and breakdown in bundles of single-wall carbon nanotubes’, Phys. Rev. B, 2001, 64, p. 241307.
    18. 18)
      • 16. Sun, J.: ‘Spin-current interaction with a monodomain magnetic body: a model study’, Phys. Rev. B, 2000, 62, p. 570.
    19. 19)
      • 18. Ashraf, R.: ‘Robust circuit & architecture design in the nanoscale regime’. PhD thesis, Portland State University, 2011.
    20. 20)
      • 21. Jasemi, M., Mirzaee, R.F., Navi, K., et al: ‘Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic’, IET Circuits Dev. Syst., 2015, 9, pp. 343352.
    21. 21)
      • 1. Zhou, Y., Thekkel, S., Bhunia, S.: ‘Low power FPGA design using hybrid CMOS-NEMS approach’. Proc. of the 2007 Int. Symp. on Low Power Electronics and Design, 2007, pp. 1419.
    22. 22)
      • 11. Behin-Aein, B., Wang, J.-P., Wiesendanger, R., et al: ‘Computing with spins and magnets’. MRS Bulletin 39.08, 2014, pp. 696702.
    23. 23)
      • 17. Xiao, J., Zangwill, A., Stiles, M.: ‘Macrospin models of spin transfer dynamics’, Phys. Rev. B, 2005, 72, p. 014446.
    24. 24)
      • 10. Zhao, W., Ben Romdhane, N., Zhang, Y., et al: ‘Racetrack memory based reconfigurable computing’. 2013 IEEE Faible Tension Faible Consommation (FTFC), 2013, pp. 14.
    25. 25)
      • 28. Chih, Y.D., Huang, C.Y., Lin, C.J., et al: ‘Adjusting reference resistances in determining MRAM resistance states’. U.S. Patent, 8,902,641, issued 2December 2014.
    26. 26)
      • 7. Zhao, W., Belhaire, E., Chappert, C., et al: ‘New non-volatile logic based on spin-MTJ’, Phys. Status Sol. (a), 2008, 205, pp. 13731377.
    27. 27)
      • 9. Zhao, W., Ravelosona, D., Klein, J., et al: ‘Domain wall shift register-based reconfigurable logic’, IEEE Trans. Magn., 2011, 47, pp. 29662969.
    28. 28)
      • 4. Kumar, T.N., Almurib, H.A., Lombardi, F.: ‘A novel design of a memristor-based look-up table (LUT) for FPGA’. 2014 IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS), 2014, pp. 703706.
    29. 29)
      • 8. Zhao, W., Chappert, C., Javerliac, V., et al: ‘High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits’, IEEE Trans. Magn., 2009, 45, pp. 37843787.
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