© The Institution of Engineering and Technology
Soft errors in semiconductor memories occur due to charged particle strikes on sensitive nodes. Technology and voltage scaling increased dramatically the susceptibility of static random access memories (SRAMs) to soft errors. In this study, the authors present AS8-SRAM, a new asymmetric memory cell that enhances the soft error resilience of SRAMs by increasing the cells critical charge. They run Simulation Program with Integrated Circuit Emphasissimulations and system level experiments to validate the AS8-SRAM cell characteristics at circuit level and evaluate the energy and reliability effectiveness of an AS8-SRAM-based cache memory. The authors’ results show that AS8-SRAM presents up to 58 times less failures in time compared to six-transistor SRAM. Moreover, based on embedded benchmarks experimentations, AS8-SRAM achieves up to 22% reduction in energy-delay product without any considerable loss in performance.
References
-
-
1)
-
20. Roche, P., Palau, J.M., Tavernier, C., et al: ‘Determination of key parameters for seu occurrence using 3-d full cell sram simulations’, IEEE Trans. Nucl. Sci., 1999, 46, (6), pp. 1354–1362 (doi: 10.1109/23.819093).
-
2)
-
7. Chakraborty, A., Homayoun, H., Khajeh, A., et al: ‘E mc2: Less energy through multi-copy cache’. Proc. 2010 Int. Conf. on Compilers, Architectures and Synthesis for Embedded Systems, ser. CASES ‘10, 2010.
-
3)
-
1. Ziegler, J.F., Curtis, H.W., Muhlfeld, H.P., et al: ‘IBM experiments in soft fails in computer electronics’, IBM J. Res. Dev., 1996, 40, (1), pp. 3–18 (doi: 10.1147/rd.401.0003).
-
4)
-
5. Guena, P.: ‘A cache primer’, , 2004.
-
5)
-
15. Jahinuzzaman, S.M., Sharifkhani, M., Sachdev, M.: ‘An analytical model for soft error critical charge of nanometric srams’, IEEE Trans. Very Large Scale Integr. Syst., 2009, 17, (9), pp. 1187–1195 (doi: 10.1109/TVLSI.2008.2003511).
-
6)
-
16. Lin, S., Kim, Y.-B., Lombardi, F.: ‘A 11-transistor nanoscale cmos memory cell for hardening to soft errors’, IEEE Trans. Very Large Scale Integr. Syst., 2011, 19, (5), pp. 900–904 (doi: 10.1109/TVLSI.2010.2043271).
-
7)
-
28. Guthaus, M.R., Ringenberg, J.S., Ernst, D., et al: ‘Mibench: A free, commercially representative embedded benchmark suite’. Proc. Workload Characterization 2001. WWC-4. 2001 IEEE Int. Workshop, 2001.
-
8)
-
25. Austin, T., Larson, E., Ernst, D.: ‘Simplescalar: an infrastructure for computer system modeling’. IEEE Computer, February 2002, vol. 35, no. 2.
-
9)
-
24. Flautner, K., Kim, N.S., Martin, S., et al: ‘Drowsy chaches: simple techniques for reducing leakage power’. IEEE Int. Symp. on Computer Architecture, ser. ISCA ‘02, 2002.
-
10)
-
21. Hazucha, P., Svensson, C.: ‘Impact of cmos technology scaling on the atmospheric neutron soft error rate’, IEEE Trans. Nucl. Sci., 2000, 47, (6), pp. 2586–2594 (doi: 10.1109/23.903813).
-
11)
-
26. Brooks, V.T.D., Martonos, D.: ‘Wattch: a framework for architecture level power analysis and optimizations’. Proc. Int. Symp. of Computer Architecture, 2000.
-
12)
-
17. Lin, S., Kim, Y.-B., Fabrizio, L.: ‘Analysis and design of nanoscale cmos storage elements for single-event hardening with multiplenode upset’, IEEE Trans. Device Mater. Reliab., 2012, 12, (1), pp. 68–77 (doi: 10.1109/TDMR.2011.2167233).
-
13)
-
3. Anghel, L., Nicolaidis, M.: ‘Cost reduction and evaluation of a temporary faults detecting technique’. Design, Automation and Test in Europe Conf. and Exhibition 2000, ser. DATE, 2000.
-
14)
-
14. Liu, X., Pan, L., Zhao, X., et al: ‘A novel soft error immunity sram cell’. IEEE Int. Integrated Reliability Workshop Final Report, 2013, ser. IRW ‘13, October 2013.
-
15)
-
23. Jahinuzzaman, S.: ‘Modeling and mitigation of soft errors in nanoscale srams’. PhD dissertation, University of Waterloo, 2008.
-
16)
-
8. Alouani, I., Niar, S., Kurdahi, F., et al: ‘Parity-based mono-copy cache for low power consumption and high reliability’. 23rd IEEE Int. Symp. on Rapid System Prototyping (RSP), 2012, October 2012.
-
17)
-
9. Argyrides, C., Pradhan, D., Kocak, T.: ‘Matrix codes for reliable and cost efficient memory chips’, IEEE Trans. Very Large Scale Integr. Syst., 2011, 19, (3), pp. 420–428 (doi: 10.1109/TVLSI.2009.2036362).
-
18)
-
19. Ishikura, S., Kurumada, M., Terano, T., et al: ‘A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous r/w access issues’, IEEE J. Solid-State Circuits, 2008, 43, (4), pp. 938–945 (doi: 10.1109/JSSC.2008.917568).
-
19)
-
20)
-
12. Torrens, G., Bota, S., Alorda, B., et al: ‘An experimental approach to accurate alpha-SER modeling and optimization through design parameters in 6T SRAM cells for deep-nanometer CMOS’, IEEE Trans. Device Mater. Reliab., 2014, 14, (4), pp. 1013–1021 (doi: 10.1109/TDMR.2014.2360035).
-
21)
-
22)
-
18. Guo, J., Xiao, L., Mao, Z.: ‘Novel low-power and highly reliable radiation hardened memory cell for 65 nm cmos technology’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2014, 61, (7), pp. 1994–2001 (doi: 10.1109/TCSI.2014.2304658).
-
23)
-
10. Gherman, V.: ‘Soft-error protection of tcams based on eccs and asymmetric sram cells’, Electron. Lett., 2014, 50, pp. 1823–1824(1) (doi: 10.1049/el.2014.2540).
-
24)
-
13. Gill, B.S., Papachristou, C., Wolff, F.G.: ‘A new asymmetric sram cell to reduce soft errors and leakage power in fpga’. Design, Automation and Test in Europe Conf. and Exhibition 2007, ser. DATE'07, April 2007.
-
25)
-
4. Reviriego, P., Maestro, J.A., Flanagan, M.F.: ‘Error detection in majority logic decoding of euclidean geometry low density parity check (eg-ldpc) codes’, IEEE Trans. VLSI Syst., 2013, 21, (1), pp. 156–159 (doi: 10.1109/TVLSI.2011.2179681).
-
26)
-
6. Gherman, V., Evain, S., Seymour, N., et al: ‘Generalized parity-check matrices for sec-ded codes with fixed parity’. IEEE 17th Int. On-Line Testing Symp. (IOLTS), 2011, July 2011, pp. 198–201.
-
27)
-
11. Nisar, M.M., Barlas, I., Roemer, M.: ‘Analysis and asymmetric sizing of cmos circuits for increased transient error tolerance’. AIAA Infotech@Aerospace 2010, Atlanta, Georgia, 2010.
-
28)
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