Your browser does not support JavaScript!

AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement

AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Soft errors in semiconductor memories occur due to charged particle strikes on sensitive nodes. Technology and voltage scaling increased dramatically the susceptibility of static random access memories (SRAMs) to soft errors. In this study, the authors present AS8-SRAM, a new asymmetric memory cell that enhances the soft error resilience of SRAMs by increasing the cells critical charge. They run Simulation Program with Integrated Circuit Emphasissimulations and system level experiments to validate the AS8-SRAM cell characteristics at circuit level and evaluate the energy and reliability effectiveness of an AS8-SRAM-based cache memory. The authors’ results show that AS8-SRAM presents up to 58 times less failures in time compared to six-transistor SRAM. Moreover, based on embedded benchmarks experimentations, AS8-SRAM achieves up to 22% reduction in energy-delay product without any considerable loss in performance.


    1. 1)
    2. 2)
      • 7. Chakraborty, A., Homayoun, H., Khajeh, A., et al: ‘E mc2: Less energy through multi-copy cache’. Proc. 2010 Int. Conf. on Compilers, Architectures and Synthesis for Embedded Systems, ser. CASES ‘10, 2010.
    3. 3)
    4. 4)
      • 5. Guena, P.: ‘A cache primer’, Application Note, Freescale Semiconductors, 2004.
    5. 5)
    6. 6)
    7. 7)
      • 28. Guthaus, M.R., Ringenberg, J.S., Ernst, D., et al: ‘Mibench: A free, commercially representative embedded benchmark suite’. Proc. Workload Characterization 2001. WWC-4. 2001 IEEE Int. Workshop, 2001.
    8. 8)
      • 25. Austin, T., Larson, E., Ernst, D.: ‘Simplescalar: an infrastructure for computer system modeling’. IEEE Computer, February 2002, vol. 35, no. 2.
    9. 9)
      • 24. Flautner, K., Kim, N.S., Martin, S., et al: ‘Drowsy chaches: simple techniques for reducing leakage power’. IEEE Int. Symp. on Computer Architecture, ser. ISCA ‘02, 2002.
    10. 10)
    11. 11)
      • 26. Brooks, V.T.D., Martonos, D.: ‘Wattch: a framework for architecture level power analysis and optimizations’. Proc. Int. Symp. of Computer Architecture, 2000.
    12. 12)
    13. 13)
      • 3. Anghel, L., Nicolaidis, M.: ‘Cost reduction and evaluation of a temporary faults detecting technique’. Design, Automation and Test in Europe Conf. and Exhibition 2000, ser. DATE, 2000.
    14. 14)
      • 14. Liu, X., Pan, L., Zhao, X., et al: ‘A novel soft error immunity sram cell’. IEEE Int. Integrated Reliability Workshop Final Report, 2013, ser. IRW ‘13, October 2013.
    15. 15)
      • 23. Jahinuzzaman, S.: ‘Modeling and mitigation of soft errors in nanoscale srams’. PhD dissertation, University of Waterloo, 2008.
    16. 16)
      • 8. Alouani, I., Niar, S., Kurdahi, F., et al: ‘Parity-based mono-copy cache for low power consumption and high reliability’. 23rd IEEE Int. Symp. on Rapid System Prototyping (RSP), 2012, October 2012.
    17. 17)
    18. 18)
    19. 19)
      • 2. Semiconductor industry association, international technology roadmap for semiconductors. Available:
    20. 20)
    21. 21)
      • 22. Predictive technology model (ptm) website. Available at:
    22. 22)
    23. 23)
    24. 24)
      • 13. Gill, B.S., Papachristou, C., Wolff, F.G.: ‘A new asymmetric sram cell to reduce soft errors and leakage power in fpga’. Design, Automation and Test in Europe Conf. and Exhibition 2007, ser. DATE'07, April 2007.
    25. 25)
    26. 26)
      • 6. Gherman, V., Evain, S., Seymour, N., et al: ‘Generalized parity-check matrices for sec-ded codes with fixed parity’. IEEE 17th Int. On-Line Testing Symp. (IOLTS), 2011, July 2011, pp. 198201.
    27. 27)
      • 11. Nisar, M.M., Barlas, I., Roemer, M.: ‘Analysis and asymmetric sizing of cmos circuits for increased transient error tolerance’. AIAA [email protected] 2010, Atlanta, Georgia, 2010.
    28. 28)
      • 27. Spec cpu2000 benchmarks. Available at:

Related content

This is a required field
Please enter a valid email address