© The Institution of Engineering and Technology
A defect-oriented built-in self-test (BIST) structure of charge-pump phase-locked loop (CP-PLL) for high fault coverage and low area overhead test solution is proposed. It employs a new structure of phase/frequency detector, a D flip-flop and some existing blocks in the PLL as the input stimulus generator and fault feature extracted devices for testing evaluation. Thus, no extra test stimulus or high-performance measured instruments are required for test. The structure is easily implemented and has a little influence on the performance of CP-PLL. Fault simulation results indicate that the proposed BIST structure has high fault coverage (98.75%) and low area overhead (0.78%).
References
-
-
1)
-
10. Amrutur, B., Das, P.K., Vasudevamurthy, R.: ‘0.84ps resolution clock skew measurement via subsampling’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2011, 19, (12), pp. 2267–2275 (doi: 10.1109/TVLSI.2010.2083706).
-
2)
-
17. Hsu, C.L., Lai, Y., Wang, S.W.: ‘Built-in self-test for phase-locked loops’, IEEE Trans. Instrum. Meas., 2005, 54, (3), pp. 996–1002 (doi: 10.1109/TIM.2005.847343).
-
3)
-
3. Dasnurkar, S.D., Abraham, J.A.: ‘PLL lock time prediction and parametric testing by lock waveform characterization’. IEEE 16th Int. Mixed-Signals, Sensors and Systems Test Workshop, 2010, pp. 1–5.
-
4)
-
9. Cai, Z.H., Xu, H., Que, S., et al: ‘On-chip long-term jitter measurement for PLL based on under-sampling technique’, IEICE Electron. Express, 2013, 10, (24), pp. 1–9 (doi: 10.1587/elex.10.20130887).
-
5)
-
8. Cheng, K.H., Liu, J.C., Chang, C.Y., et al: ‘Built-in jitter measurement circuit with calibration techniques for a 3-GHz clock generator’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2011, 19, (8), pp. 1325–1335 (doi: 10.1109/TVLSI.2010.2052377).
-
6)
-
19. Tiwari, A., Sahu, A.K.: ‘An innovative approach of computational fault detection using design for testability of CP-PLL’. Proc. of National Conf. on Computing & Communications Systems, 2012, pp. 1–6.
-
7)
-
20. Tiwari, S., Shu, A.K., Sinha, G.R.: ‘Design for testability architecture using the existing elements of CP-PLL for digital testing application in VLSI ASCI design’, Int. J. VLSI Signal Process. Appl., 2012, 2, (1), pp. 56–64.
-
8)
-
1. Fischette, D.M., Loke, A.L.S., DeSantis, R.J., et al: ‘An embedded all-digital circuit to measure PLL response’, IEEE J. Solid-State Circuits, 2010, 45, (8), pp. 1492–1503 (doi: 10.1109/JSSC.2010.2048143).
-
9)
-
22. Xia, L.H., Wu, J.H., Zhang, M.: ‘A methodology of fault detection using design for testability of CP-PLL loops’. The 20th Asia-Pacific Conf. on Communications, 2014, pp. 161–165.
-
10)
-
13. Kim, S., Soma, M.: ‘An all-digital built-in self-test for high-speed phase-locked loops’, Trans. IEEE Circuits Syst. II, Analog Digit. Signal Process., 2001, 48, (2), pp. 141–150 (doi: 10.1109/82.917782).
-
11)
-
5. Kim, J.: ‘On-chip measurement of jitter transfer and supply sensitivity of PLL/DLLs’, IEEE Trans. Circuits Syst. II, 2009, 56, (6), pp. 449–453 (doi: 10.1109/TCSII.2009.2020941).
-
12)
-
12. Seongwon, K., Soma, M.: ‘Test evaluation and data on defect-oriented BIST architecture for high-speed PLL’. Proc. of Test Conf., 2001, pp. 830–837.
-
13)
-
18. Hsu, C.L., Lai, Y.: ‘Low-cost CP-PLL DFT structure implementation for digital testing application’, IEEE Trans. Instrum. Meas., 2009, 58, (6), pp. 1897–1905 (doi: 10.1109/TIM.2008.2005852).
-
14)
-
14. Azais, F., Bertrand, Y., Renovell, M., et al: ‘An all-digital DFT scheme for testing catastrophic faults in PLLs’, IEEE Des. Test Comput., 2003, 20, (1), pp. 60–67 (doi: 10.1109/MDT.2003.1173054).
-
15)
-
7. Wang, P.Y., Chang, H.M., Cheng, K.T.: ‘An all-digital built-in self-test technique for transfer function characterization of RF PLLs’. IEEE Design, Automation & Test in Europe Conf., 2011, pp. 1–6.
-
16)
-
11. Kinger, R., Narasimhawsamy, S., Sunter, S.: ‘Experiences with parametric BIST for production testing PLLs with picosecond precision’. IEEE Int. Test Conf. (ITC), 2010, pp. 1–9.
-
17)
-
2. Hsiao, S.-W., Tzou, N., Chatterjee, A.: ‘A programmable BIST design for PLL static phase offset estimation and clock duty cycle detection’. IEEE 31st VLSI Test Symp. (VTS), 2013, pp. 1–6.
-
18)
-
15. dasnurkar, S.D., Abraham, J.A.: ‘Frequency-independent parametric built in test solution for PLLs with low speed test resources’. The 18th Int. Mixed-Signals, Sensors and Systems Test Workshop, 2012, pp. 73–78.
-
19)
-
6. Kho, J., Lim, S.G., Tan, Y.L., et al: ‘An enhanced high-precision and time-saving jitter transfer measurement’. IEEE Symp. on Electrical Design of Advanced Packaging & Systems, 2009, pp. 1–4.
-
20)
-
4. Hsiao, S.-W., Wang, X., Chatterjee, A.: ‘Analog sensor based testing of phase-locked loop dynamic performance parameters ‘. The 22nd Asian Test Symp. (ATS), 2013, pp. 50–55.
-
21)
-
16. Toihria, I., Ayadi, R., Masmoudi, M.: ‘High performance BIST PLL approach for VCO testing’. The 1st Int. Conf. on Advanced Technologies for Signal and Image Processing (ATSIP), 2014, pp. 517–522.
-
22)
-
21. Xia, L.H., Wu, J.H., Zhang, M.: ‘An all-digital built-in self-test for charge-pump phase-locked loops’. IEEE 8th Int. Symp. on WISP, 2013, pp. 97–102.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2015.0224
Related content
content/journals/10.1049/iet-cds.2015.0224
pub_keyword,iet_inspecKeyword,pub_concept
6
6