access icon free Concurrent optimisation method for three-dimensional power delivery network design

Power distribution network (PDN) design in three-dimensional integrated circuit (3D IC) is one of the most important challenges. Power wires and power bumps or power through-silicon-vias (TSVs) are the two major factors that affect the voltage as the IR-drop of 3D ICs. Different parameters of power wires and different insertions of power bumps/TSVs cause different IR-drop distribution. In this study, the authors propose 3D power concurrent optimisation to achieve a multi-objective design for 3D IC PDN, which optimises the insertion of power bumps/TSVs according to the IR-drop distribution and concurrently reduces the power wire's routing area so as to lower the metal coverage rate, guaranteeing the IR-drop and other constraints. Results of the experiments show that the proposed method can get more solutions than one after a run with both less power routing area and less number of power bumps/TSVs. In addition, the experiments also show that it is more effective and efficient than the classical exhaustive method.

Inspec keywords: wires (electric); three-dimensional integrated circuits; distribution networks; optimisation

Other keywords: power wires; 3D IC; 3D power concurrent optimisation; power distribution network; power bumps; PDN; metal coverage rate; three-dimensional integrated circuit; IR-drop distribution; power through-silicon-vias; TSV; three-dimensional power delivery network design; multiobjective design

Subjects: Optimisation techniques; Semiconductor integrated circuit design, layout, modelling and testing; Wires and cables

References

    1. 1)
      • 1. Jung, M., Lim, S.K.: ‘A study of IR-drop noise issues in 3D ICs with through-silicon-vias’. IEEE Int. Conf. on 3D System Integration, Munich, Germany, November 2010, pp. 17.
    2. 2)
    3. 3)
    4. 4)
      • 24. Kouroussis, D., Najm, F.N.: ‘A static pattern-independent technique for power grid voltage integrity verification’. Proc. of Conf. on Design Automation, Anaheim, CA, June 2003, pp. 99104.
    5. 5)
    6. 6)
      • 10. Chen, H.-T., Lin, H.-L., Wang, Z.-C.: ‘A new architecture for power network in 3D IC’. Proc. of Design, Automation and Test in Europe, Grenoble, France, March 2011, pp. 16.
    7. 7)
      • 11. Chowdhury, S.: ‘Optimum design of reliable IC power networks having general graph topologies’. Proc. of Design Automation Conf., Las Vegas, NV, June 1989, pp. 787790.
    8. 8)
      • 6. Cheng, C.-H., Kuo, C.-H., Huang, S.-H.: ‘TSV number minimization using alternative paths’. IEEE Int. Conf. on Integrated Circuit Design and Technology, Kaohsiung, Taiwan, May 2011, pp. 14.
    9. 9)
    10. 10)
      • 17. Khan, N.H., Reda, S., Hassoun, S.: ‘Early estimation of TSV area for power delivery in 3-d integrated circuits’. IEEE Conf. on 3D System Integration, Munich, Germany, November 2010, pp. 16.
    11. 11)
      • 12. Knechtel, J., Markov, I.L., Lienig, J., et al: ‘Multiobjective optimization of deadspace, a critical resource for 3D-IC integration’. IEEE ACM Int. Conf. on Computer-Aided Design, Digest of Technical Papers, San Jose, CA, November 2012, pp. 705712.
    12. 12)
    13. 13)
      • 4. Wang, J., Lu, X., Qiu, W., et al: ‘Static compaction of delay tests considering power supply noise’. IEEE Proc. of Symp. on VLSI Test, Palm Springs, CA, May 2005, pp. 235240.
    14. 14)
      • 18. Kim, D.H., Athikulwongse, K., Lim, S.K.: ‘A study of through-silicon-via impact on the 3D stacked IC layout’. IEEE ACM Int. Conf. on Computer-Aided Design, Digest of Technical Papers, San Jose, CA, November 2009, pp. 674680.
    15. 15)
    16. 16)
    17. 17)
    18. 18)
      • 9. Su, H., Gala, K., Sapatnekar, S.S.: ‘Fast analysis and optimization of power/ground networks’. IEEE ACM Int. Conf. on Computer-Aided Design, Digest of Technical Papers, San Jose, CA, November 2000, pp. 477482.
    19. 19)
    20. 20)
      • 16. Xu, Z., Lu, J.-Q., Webb, B.C., et al: ‘Electromagnetic-SPICE modeling and analysis of 3D power network’. Proc. of Conf. on Electronic Components and Technology, Lake Buena Vista, FL, May 2011, pp. 21712178.
    21. 21)
      • 19. Tseng, T.-W., Lin, C.-T., Lee, C.-H., et al: ‘A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage’. Proc. of Int. Symp. on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 2014, pp. 14.
    22. 22)
      • 8. Wang, S., Firouzi, F., Oboril, F., et al: ‘P/G TSV planning for IR-drop reduction in 3D-ICs’. Proc. of Design, Automation and Test in Europe, Dresden, Germany, March 2014, p. 44.
    23. 23)
    24. 24)
      • 25. Hung, W.-L., Link, G.M., Xie, Y., et al: ‘Interconnect and thermal-aware floorplanning for 3D microprocessors’. Proc. of Int. Symp. on Quality Electronic Design, San Jose, CA, March 2006, pp. 6104.
    25. 25)
      • 5. Ahmed, M.A., Chrzanowska-Jeske, M.: ‘Delay and power optimization with TSV-aware 3D floorplanning’. Proc. of Int. Symp. on Quality Electronic Design, Santa Clara, CA, March 2014, pp. 189196.
    26. 26)
      • 7. Falkenstern, P., Xie, Y., Chang, Y.-W., et al: ‘Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis’. Proc. of Conf. on the Asia and South Pacific Design Automation, Taipei, Taiwan, January 2010, pp. 169174.
    27. 27)
    28. 28)
      • 26. Tan, X.-D.S., Shi, C.-J.R.: ‘Fast power/ground network optimization based on equivalent circuit modeling’. Proc. of Conf. on Design Automation, Las Vegas, NV, June 2001, pp. 550554.
    29. 29)
    30. 30)
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2015.0112
Loading

Related content

content/journals/10.1049/iet-cds.2015.0112
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading