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Dataflow object detection system for FPGA-based smart camera

Dataflow object detection system for FPGA-based smart camera

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Embedded computer vision based smart systems raise challenging issues in many research fields, including real-time vision processing, communication protocols or distributed algorithms. The amount of data generated by cameras using high resolution image sensors requires powerful computing systems to be processed at digital video frame rates. Consequently, the design of efficient and flexible smart cameras, with on-board processing capabilities, has become a key issue for the expansion of smart vision systems relying on decentralised processing at the image sensor node level. In this context, field programmable gate arrays (FPGA)-based platforms, supporting massive data parallelism, offer large opportunities to match real-time processing constraints compared with platforms based on general purpose processors. In this study, the authors describe the implementation, on such a platform, of a configurable object detection application, reformulated according to the dataflow model of computation. The application relies on the computation of the histogram of oriented gradients and a linear SVM-based classification. It is described using the CAPH programming language, allowing efficient hardware descriptions to be generated automatically from high level dataflow specifications without prior knowledge of hardware description languages such as VHDL or Verilog. Results show that the performance of the generated code does not suffer from a significant overhead compared with handwritten HDL code.

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