© The Institution of Engineering and Technology
Continuous-time (CT) delta-sigma (Δ∑) analog-to-digital converters (ADCs) have one important constrain, namely the excess loop delay. Most excess loop delay compensation methods need to know the exact value of the excess loop delay in advance. However, the value of the excess loop delay is a uniformly distributed random variable. To improve system performance with the same loop filter, a new compensation algorithm for the excess loop delay of CT Δ∑ ADCs based on the model matching method is presented in this study. Compared with previous compensation methods, the model matching algorithm is more practical because the value of the excess loop delay varies randomly every clock period. It is shown through simulation that a mean value based algorithm can improve the SQNR performance of CT Δ∑ ADCs for the most probable values of the excess loop delay.
References
-
-
1)
-
7. Schoofs, R., Eeckelaert, T., Steyaert, M., Gielen, G., Sansen, W.: ‘A continuous-time delta-sigma modulator for 802.11a/b/g WLAN implemented with a hierarchical bottom-up optimization methodology’. 13th IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS'06., 2006, pp. 950–953.
-
2)
-
12. Gao, W., Shoaei, O., Snelgrove, W.M.: ‘Excess loop delay effects in continuous-time delta-sigma modulators and the compensation solution’. Proc. of 1997 IEEE Int. Symp. on Circuits and Systems, 1997. ISCAS'97, , 1997, vol. 1, pp. 65–68.
-
3)
-
24. Aguirre, P., Camargo, V., Klimach, H., Susin, A., Prior, C.: ‘Behavioral modeling of continuous-time modulators in matlab/simulink’. IEEE Fourth Latin American Symp. on Circuits and Systems (LASCAS), 2013, pp. 1–4.
-
4)
-
14. De Vuyst, B., Rombouts, P., De Maeyer, J., Gielen, G.: ‘The nyquist criterion: a useful tool for the robust design of continuous-time ∑Δ modulators’, IEEE Trans. Circuits Syst. II: Express Briefs, 2010, 57, (6), pp. 416–420 (doi: 10.1109/TCSII.2010.2048368).
-
5)
-
8. Chan, K.T., Martin, K.W.: ‘Components for a GaAs delta-sigma modulator oversampled analog-to-digital converter’. Proc. IEEE Int. Sympos. on Circuits and Systems, 1992. ISCAS'92., 1992, vol. 3, pp. 1300–1303.
-
6)
-
21. Weng, C.H., Lin, C.C., Chang, Y.C., Lin, T.H.: ‘A 0.89-mW 1-MHz 62-dB SNDR continuous-time delta-sigma modulator with an asynchronous sequential quantizer and digital excess-loop-delay compensation’, IEEE Trans. Circuits Syst. II: Express Briefs, 2011, 58, (12), pp. 867–871 (doi: 10.1109/TCSII.2011.2172709).
-
7)
-
2. Afifi, M., Keller, M., Manoli, Y., Ortmanns, M.: ‘Excess loop delay compensation technique for tunable bandpass delta sigma modulators’. 52nd IEEE Int. Midwest Symp. on Circuits and Systems, MWSCAS'09., 2009, pp. 365–368.
-
8)
-
18. Cai, C.Y., Jiang, Y., Sin, S.W., U, S.P., Martins, R.P.: ‘A passive excess-loop-delay compensation technique for Gm-C based continuous-time ∑Δ modulators’. IEEE 54th Int. Midwest Symp. on Circuits and Systems (MWSCAS), 2011, pp. 1–4.
-
9)
-
17. Li, R., Li, J., Yi, T., Hong, Z., Liu, B.Y.: ‘A 18 mW 20-MHz continuous-time Δ∑ modulator for LTE communication system with power efficient multi-stage amplifier’. IEEE Int. Symp. on Radio-Frequency Integration Technology (RFIT), 2011, pp. 113–116.
-
10)
-
23. Y Kimura, A.Y.M.Y.: ‘Continuous-time delta-sigma modulator using vector filter in feedback path to reduce effect of clock jitter and excess loop delay’, Analog Integr. Circuits Signal Process., 2013, 75, pp. 279–286 (doi: 10.1007/s10470-013-0038-6).
-
11)
-
3. El-Sankary, K., Alamdari, H.H., El-Masry, E.I.: ‘An adaptive ELD compensation technique using a predictive comparator’, IEEE Trans. Circuits Syst. II: Express Briefs,2009, 56, (8), pp. 619–623 (doi: 10.1109/TCSII.2009.2025620).
-
12)
-
10. Adams, R.W.: ‘Design and implementation of an audio 18-bit analog-to-digital converter using oversampling techniques’, J. Audio Eng. Soc., 1986, 34, pp. 153–166.
-
13)
-
26. Hernández, L., Wiesbauer, A., Patón, S., Di Giandomencio, A.: ‘Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction’. Proc. of the 2004 Int. Symp. on Circuits and Systems, ISCAS'04.2004, vol. 1, pp. I–1072–5.
-
14)
-
11. Lee, H.J.: ‘The effects of excess loop delay in continuous-time delta-sigma modulators’. , 2005.
-
15)
-
19. Ding, C., Zou, L., Keller, M., Manoli, Y.: ‘Approaches to digital compensation of excess loop delay in continuous-time Delta-Sigma modulators using a scaled quantizer’. IEEE Int. Symp. on Circuits and Systems (ISCAS), 2012, pp. 3001–3004.
-
16)
-
13. Keller, M., Buhmann, A., Sauerbrey, J., Ortmanns, M., Manoli, Y.: ‘A comparative study on excess-loop-delay compensation techniques for continuous-time sigma-delta modulators’, IEEE Trans. Circuits Syst. I: Regular Papers, , 2008, 55, (11), pp. 3480–3487 (doi: 10.1109/TCSI.2008.925362).
-
17)
-
20. Huang, J.F., Lin, Y.J., Huang, K.C., Liu, R.Y.: ‘A CT sigma-delta modulator with a hybrid loop filter and capacitive feedforward’. IEEE 54th Int. Midwest Symp. on Circuits and Systems (MWSCAS), 2011, pp. 1–4.
-
18)
-
16. Kauffman, J.G., Witte, P., Lehmann, M., Becker, J., Manoli, Y., Ortmanns, M.: ‘A 72 dB DR, CT delta sigma modulator using digitally estimated, auxiliary DAC linearization achieving 88 fJ/conv-step in a 25 MHz BW’, IEEE J. Solid-State Circuits, 2014, 49, (2), pp. 392–404 (doi: 10.1109/JSSC.2013.2289887).
-
19)
-
1. Yan, S., Sanchez-Sinencio, E.: ‘A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth’, IEEE J. Solid-State Circuits, 2004, 39, (1), pp. 75–86 (doi: 10.1109/JSSC.2003.820856).
-
20)
-
5. Honarparvar, M., Aghdam, E.N.: ‘Dual mode reconfigurable continuous time delta-sigma modulator for GS M/WCDMA standards’. 20th Iranian Conf. on Electrical Engineering (ICEE), 2012, pp. 211–216.
-
21)
-
25. Candy, J.C., Temes, G.C.: ‘Oversampling delta-sigma data converters: theory, design, and simulation’ (Wiley-IEEE Press, 1991, 1st ed.).
-
22)
-
22. Chen, C.T.: ‘Linear system theory and design’ (Oxford University Press, New Yourk, Oxford, 1999).
-
23)
-
9. Nary, K.R., Beccue, S., Nubling, R., et al: ‘Second order delta sigma modulators using AlGaAs/GaAs HBTS’. 16th Annual Gallium Arsenide Integrated Circuit (GaAs IC) Symp., 1994. Technical Digest 1994, 1994, pp. 232–235.
-
24)
-
1. Cherry, J., Snelgrove, W.: ‘Excess loop delay in continuous time delta sigma modulators’, IEEE Trans. Circuits Syst., 1999, 46, (4), pp. 376–389 (doi: 10.1109/82.755409).
-
25)
-
15. De Vuyst, B., Rombouts, P., Gielen, G.: ‘A rigorous approach to the robust design of continuous-time ∑Δ modulators’, IEEE Trans. Circuits Syst. I: Regul. Pap., 2011, 58, (12), pp. 2829–2837 (doi: 10.1109/TCSI.2011.2158702).
-
26)
-
6. Aboushady, H., Louerat, M.M.: ‘Loop delay compensation in bandpass continuous-time Sigma; Delta; modulators without additional feedback coefficients’. Proc. of the 2004 Int. Symp. on Circuits and Systems, ISCAS'04, 2004, vol. 1, pp. I–1124–7.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2014.0368
Related content
content/journals/10.1049/iet-cds.2014.0368
pub_keyword,iet_inspecKeyword,pub_concept
6
6