access icon free Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells

Modern digital circuits are facing aggressive technology and voltage scaling under emerging technology generations. This study proposes a circuit-level technique to mitigate the adverse effects of process, voltage and temperature (PVT) variations on the design metrics of full adder (FA) cells under such ultra-deep sub-micron technology nodes. The proposed FA cells exhibit improved variability because of the use of inverting low voltage Schmitt trigger sub-circuits incorporated in the designs in place of inverters. The proposed circuits have been designed to operate in the near-threshold region, which offers a trade-off between performance and power consumption. The comparative analysis based on Monte Carlo simulations in a SPICE environment, using the 16-nm complementary metal-oxide semiconductor predictive technology model, demonstrates that the proposed technique is capable of mitigating the impact of PVT variations on major design metrics such as power, delay and power-delay product in FA cells. This improvement is achieved at the expense of two extra transistors for every replaced inverter in the FA cell.

Inspec keywords: logic gates; logic design; CMOS logic circuits; trigger circuits; adders

Other keywords: aggressive technology; digital circuits; power consumption; FA cells; complementary metal-oxide semiconductor predictive technology model; voltage scaling; SPICE environment; PVT variations; inverting low voltage Schmitt trigger sub-circuits; full adder cell design metric; size 16 nm; complementary metal-oxide semiconductor full adder cells; process voltage and temperature variation impact mitigation; circuit-level design technique; Monte Carlo simulations; power-delay product; ultra-deep sub-micron technology nodes; near-threshold region

Subjects: Logic circuits; Digital circuit design, modelling and testing; Logic design methods; Logic elements; Logic and switching circuits; CMOS integrated circuits

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http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2014.0167
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