The two implementation choices for the baseband part of wireless radios are the application-specific platforms (e.g. application-specific integrated circuits (ASICs)) and the programmable processors (e.g. digital signal processors (DSPs)). An application-specific instruction-set processor (ASIP) is a customised processor that bridges the gap between the two platforms. In this work, a novel implementation of the signal processing part of an orthogonal frequency division multiplexing (OFDM) baseband processor using three ASIPs is presented. The ASIPs provide novel architectures for the symbol chain, including fast Fourier transform, channel estimation subsystem and synchronisation subsystem. This design provides a close to DSPs level of flexibility, making it suitable for supporting all the modes of a large number of OFDM standards. In the meantime, the system maintains a performance level comparable to ASICs. This is demonstrated by providing post-layout results for 0.13 μm Taiwan semiconductor manufacturing company complementary metal-oxide semiconductor technology.

References

1. 1)
  - 17. Guan, X., Lin, H., Fei, Y.: ‘Design of an application-specific instruction set processor for high-throughput and scalable FFT’. IEEE Int. Symp. Circuits and Systems (ISCAS), May 2009, pp. 2513–2516.
2. 2)
  - 13. Said, M., Nasr, O., Shalash, A.: ‘Embedded reconfigurable synchronization acquisition ASIP for a multi-standard OFDM receiver’, EURASIP J. Embedded Syst., 2012, 2012, (1), pp. 1–16. [Online]. Available at: http://dx.doi.org/10.1186/1687-3963-2012-2 (doi: 10.1186/1687-3963-2012-1).
3. 3)
  - J.W. Cooley , J.W. Tukey . An algorithm for the machine calculation of complex fourier series. Math. Comput. , 297 - 301
4. 4)
  - 10. Hassan, H.M., Shalash, A.F., Mohamed, K.: ‘FPGA implementation of an ASIP for high throughput DFT/DCT 1D/2D engine’. IEEE Int. Symp. Circuits and Systems (ISCAS) 2011, 2011.
5. 5)
  - 9. Hassan, H.M., Shalash, A.F., Hamed, H.M.: ‘Design architecture of generic DFT/DCT 1D and 2D engine controlled by SW instructions’. Asia Pacific Conf. Circuits and Systems APCCAS 2010, 2010.
6. 6)
  - 18. Braganza, S., Leeser, M.: ‘The 1D discrete cosine transform for large point sizes implemented on reconfigurable hardware’. IEEE Int. Conf. Application-Specific Systems, Architectures and Processors ASAP, July 2007, pp. 101–106.
7. 7)
  - 21. Hanan, K.M., Hassan, M., Shalash, A.F.: ‘Implementation of a reconfigurable ASIP for high throughput low power DFT/DCT/FIR engine’, EURASIP J. Embedded Syst., 2012, 2012. [Online]. Available at: http://dx.doi.org/10.1186/1687-3963-2012-3.
8. 8)
  - 24. Troya, A., Maharatna, K., Krstic, M., Grass, E.: ‘Low-power VLSI implementation of the inner receiver for OFDM based WLAN systems’, IEEE Trans. Circuits Syst., 2008, 55, p. 672 (doi: 10.1109/TCSI.2007.913732).
9. 9)
  - 23. Harju, L., Nurmi, J.: ‘A synchronization coprocessor architecture for WCDMA/OFDM mobile terminal implementations’. Int. Symp. System-on-Chip, November 2005, pp. 141–145.
10. 10)
  - 14. Dawid, H., Meyr, H.: ‘CORDIC algorithms and architectures’, Digit. Signal Process. Multim. Syst., 1999, p. 623655.
11. 11)
  - A.S.Y. Poon . An energy-efficient reconfigurable baseband processor for wireless communications. IEEE Trans. VLSI Syst. , 3 , 319 - 327
12. 12)
  - 25. Zhong, G., Xu, F., Willson, A.N.Jr.: ‘A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring’, IEEE J. Solid-State Circuits (JSSC), 2006, 41, pp. 483–495 (doi: 10.1109/JSSC.2005.862344).
13. 13)
  - 12. Hamdy, M., Nasr, O., Shalash, A.: ‘Design and implementation of a reconfigurable ASIP for OFDM channel estimation’, 2013.
14. 14)
  - 22. Li, X., Zheng, Y., Lai, Z.: ‘A low complexity sign ML detector for symbol and frequency synchronization of OFDM systems’, IEEE Trans. Consum. Electron., 2006, 52, pp. 317–320 (doi: 10.1109/TCE.2006.1649644).
15. 15)
  - 19. Lee, D.H., Kim, S.C., Park, D.C., il Kim, Y.: ‘A comparative study of channel estimation for mobile WIMAX system in high mobility’. Int. Conf. Advanced Communication Technology, April 2009, pp. 781–785.
16. 16)
  - 16. Jacobson, A.T., Truong, D.N., Baas, B.M.: ‘The design of a reconfigurable continuous-flow mixed-radix FFT processor’. IEEE Int. Symp. Circuits and Systems (ISCAS), June 2009, pp. 1133–1136.
17. 17)
  - 2. Hangpei, T., Deyuan, G., Yian, Z.: ‘Gaining flexibility and performance of computing using application-specific instructions and reconfigurable architecture’. Int. J. Hybrid Information Technology, April 2009, vol. 2.
18. 18)
  - 4. Iacono, D.L., Zory, J., Messina, E., Piazzese, N., Saia, G., Bettinelli, A.: ‘ASIP architecture for multi-standard wireless terminals’. Design, Automation and Test in Europe (DATE ‘06), 2006.
19. 19)
  - 20. Hanzo, L., Keller, T., Muenster, M., Choi, B.-J.: ‘OFDM and MC-CDMA for broadband multi-user communications, WLANs and broadcasting’ (Wiley, New York, NY, USA, 2003).
20. 20)
  - 5. Nilsson, A., Tell, E., Liu, D.: ‘An 11 mm2, 70 mw fully programmable baseband processor for mobile WiMAX and DVB-T/H in 0.12 μm CMOS’, in IEEE J. Solid-State Circuits, 2009, 44, (41), pp. 520–525.
21. 21)
  - 27. Lee, Y.-H., Yu, T.-H., Huang, K.-K., Wu, A.-Y.: ‘Rapid IP design of variable-length cached-FFT processor for OFDM-based communication systems’. IEEE Workshop on Signal Processing Systems Design and Implementation, 2006. SIPS ‘06, 2006, pp. 62–65.
22. 22)
  - 11. Hamdy, M., Nasr, O., Shalash, A.: ‘ASIP design of a reconfigurable channel estimator for OFDM systems’. 2011 Int. Conf. Microelectronics (ICM), December 2011, pp. 1–5.
23. 23)
  - 7. Lin, J.-M., Yu, H.-Y., Wu, Y.-J., Ma, H.-P.: ‘A power efficient baseband engine for multiuser mobile MIMOOFDMA communications’, IEEE Trans. Circuits Syst. I, 2010, 57, (7), pp. 1779–1792 (doi: 10.1109/TCSI.2009.2034884).
24. 24)
  - 8. Abdelall, M., Shalash, A.F., Fahmy, H.A.H.: ‘A reconfigurable baseband processor for wireless OFDM synchronization sub-system’. IEEE Int. Symp. Circuits and Systems (ISCAS), 2011.
25. 25)
  - 6. Chang, C.-C., Su, C.-H., Wu, J.-M.: ‘A low power baseband OFDM receiver IC for fixed WiMAX communication’. IEEE Asian Solid-State Circuits Conference, 2007. ASSCC ‘07, 2007, pp. 292–295.
26. 26)
  - 30. Zou, H., Daneshrad, B.: ‘32 mW Self-contained OFDM receiver ASIC for mobile cellular applications’. Digest of Technical Papers. Symposium on VLSI Circuits, 2004, pp. 148–151.
27. 27)
  - 1. Boyapati, H., Kumar, R.V.R.: ‘A comparison of DSP, ASIC, and RISC DSP based implementations of multiple access in LTE’. 2010 Fourth Int. Symp. Communications, Control and Signal Processing (ISCCSP), March 2010, pp. 1–5.
28. 28)
  - 26. Weidong, L., Wanhammar, L.: ‘A pipeline FFT processor’. IEEE Workshop on Signal Processing Systems, 1999. SiPS 99, 1999, vol. 19, pp. 654–662.
29. 29)
  - 28. Tell, E., Nilsson, A., Liu, D.: ‘A programmable DSP core for baseband processing’. The Third Int. IEEE-NEWCAS Conference, June 2005, pp. 403–406.
30. 30)
  - 29. Azar, C., Ojail, M., Chevobbe, S., David, R.: ‘CERA: a channel estimation reconfigurable architecture’. Int. Conf. Telecommunications (ICT), April 2010, pp. 957–964.

Design and implementation of application-specific instruction-set processor design for high-throughput multi-standard wireless orthogonal frequency division multiplexing baseband processor

References

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