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access icon free Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer

© The Institution of Engineering and Technology
Received 25/09/2012, Accepted 12/04/2013, Revised 08/04/2013, Published

In this paper, we have proposed a novel scheduling scheme for generating continuous input-blocks for the succeeding processing units of parallel structure to achieve 100% hardware utilisation efficiency (HUE) without block folding. Based on the proposed scheme, we have derived a parallel and pipeline structure for multilevel lifting two-dimensional discrete wavelet transform (DWT). The proposed structure involves regular data-flow and does not require frame-buffer, and calculates DWT levels concurrently. A theoretical comparison shows that the proposed structure for J = 2 involves 1.25 times more multipliers and adders, 2N more registers than those of existing folded block-based structure and offers 1.25 times higher throughput, where N is the input-image width. Compared with similar existing parallel structure, the proposed structure requires the same number of multipliers and adders, 2.125N less registers and offers the same throughput rate. Application specific integrated circuit synthesis result shows that the core of the proposed structure for 2-level DWT and image size (512 × 512) involves 41% less area-delay-product and 36% less energy-per-image than those of similar existing parallel structure.

Inspec keywords: discrete wavelet transforms; scheduling; adders; application specific integrated circuits; image coding; data compression

Other keywords: image size; area-delay-product; hardware utilisation efficiency; multilevel lifting two-dimensional discrete wavelet transform; continuous input-blocks; pipeline structure; multipliers; image compression; adders; regular data-flow; multilevel lifting two-dimensional DWT; processing units; registers; parallel structure; scheduling-scheme; ASIC synthesis; 2-level DWT; HUE; input-image width

Subjects: Logic circuits; Integral transforms; Integral transforms; Computer vision and image processing techniques; Mixed analogue-digital circuits; Image and video coding; Logic and switching circuits

References

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