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Low-power 6-GHz wave-pipelined 8b × 8b multiplier

Low-power 6-GHz wave-pipelined 8b × 8b multiplier

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In this study, a low-power, high-speed, layout-efficient 8b × 8b unsigned parallel multiplier based on pair-wise algorithm with wave-pipelining is introduced. Simplified interconnection and data propagation in forward direction with no feedback in pair-wise multiplication technique is the key to achieve high-performance wave-pipelined multiplier. In the proposed work, normal process complementary pass-transistor logic is used to build all the leaf cells of combinational block. The input/output registers are designed with high-performance pulse-triggered true single-phase clocking flip flop. Post-layout simulation with Taiwan Semiconductor Manufacturing Company Limited 0.18 µm single-poly double-metal complimentary metal oxide semiconductor technology using Tanner EDA V.13 shows that the proposed multiplier works at 6.25 GHz clock frequency and achieves the throughput of 6.25 billion multiplications per second with average power dissipation of 18.54 mW and overall latency of 3.24 ns at 25°C temperature and at 2 V supply rail.

References

    1. 1)
      • 1. Khatibzadeh, A., Raahemifar, K., Ahamdi, M.: ‘A novel multiplier for high-speed applications’. Proc. IEEE Int. Conf. on SOC, Herndon, VA, December 2005, pp. 305308.
    2. 2)
      • 2. Tu, J.-H., Van, L.-D.: ‘Power-efficient pipelined reconfigurable fixed-width Baugh–Wooley multipliers’, IEEE Trans. Comput., 2009, 58, (10), pp. 13461355 (doi: 10.1109/TC.2009.89).
    3. 3)
      • 3. Aguirre-Hernandez, M., Linares-Aranda, M.: ‘Energy-efficient high-speed CMOS pipelined multiplier’. Fifth Int. Conf. on Electrical Engineering, Computing Science and Automatic Control (CCE 2008), December 2008, pp. 460464.
    4. 4)
      • 4. Liang, Y.-C., Huang, C.-J., Yang, W.-B.: ‘A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage’. IEEE Asian Solid-State Circuit Conf., Fukuoka, Japan, November 2008, pp. 7376.
    5. 5)
      • 5. Aguirre, M., Salim, M., Linares, M.: ‘Design of a 3.3-V 1.2-GHz pipelined multiplier to implement energy-efficient multimedia applications’. 48th Midwest Symp. on Circuits and Systems, August 2005, pp. 14021405.
    6. 6)
      • 6. Srinivasan, V., Ha, D.S., Sulistyo, J.B.: ‘Gigahertz-range MCML multiplier architectures’. IEEE Int. Symp. on Circuits and Systems, May 2004, vol. II, pp. 785788.
    7. 7)
      • 7. Wang, J.-S., Yang, P.-H.: ‘Power analysis and implementation of a low-power 300-MHz 8-b × 8-b pipelined multiplier’. Proc. ASP-DAC, January 2000, pp. 225228.
    8. 8)
      • 8. Ghosh, D., Nandy, S.K.: ‘Design and realization of high-performance wave-pipelined 8 × 8b multiplier in CMOS technology’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 1995, 3, (1), pp. 3648 (doi: 10.1109/92.365452).
    9. 9)
      • 9. Tatapudi, S.B., Delgado-Frias, J.G.: ‘A high performance hybrid wave-pipelined multiplier’. Proc. IEEE Computer Society Annual Symposium on VLSI, May 2005.
    10. 10)
      • 10. Burleson, W.P., Ciesielski, M., Klass, F., Liu, W.: ‘Wave-pipelining: a tutorial and research survey’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 1998, 6, (3), pp. 464474 (doi: 10.1109/92.711317).
    11. 11)
      • 11. Maity, H.K., Sarkar, M.B., Chakrobarty, A.: ‘Wave Pipelining: an analysis for high performance digital circuits’, Int. J. Electron. Eng. Res., 2009, 1, (3), pp. 269278.
    12. 12)
      • 12. Raj, A., Kayalvizhi, N.: ‘High throughput multipliers using delay equalization’, Int. J. Comput. Appl., 2010, 2, (4), pp. 913.
    13. 13)
      • 13. Wong, D., Micheli, G.D., Flynn, M.: ‘Inserting active delay elements to achieve wave-pipelining’. Proc. IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, November 1989, pp. 270273.
    14. 14)
      • 14. Tang, R., Kim, Y.-B.: ‘A novel delay balancing methodology for wave pipelined circuits’. 48th Midwest Symp. on Circuits and Systems, 7–10 August 2005, vol. 2, pp. 10351038.
    15. 15)
      • 15. Ghosh, D., Nandy, S.K., Prthasarathy, K., Visvanathan, V.: ‘NPCPL: normal process complementary pass transistor logic for low latency, high throughput designs’. IEEE Sixth Int. Conf. on VLSI Design, January 1993, pp. 341346.
    16. 16)
      • 16. Wang, J., Yang, P., Sheng, D.: ‘Design of a 3-V 300-MHz low-power 8-b × 8-b pipelined multiplier using pulse-triggered TSPC flip-flops’, IEEE J. Solid-State Circuits, 2000, 35, (4), pp. 583592 (doi: 10.1109/4.839918).
    17. 17)
      • 17. Affendi, B., Takahashi, A.: ‘Reduction on the uses of intermediate registers for pipelined circuits’. SASIMI Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, Japan, October 2004, pp. 333338.
    18. 18)
      • 18. Cotten, L.: ‘Maximum rate pipelined systems’. Proc. AFIPS Spring Joint Computer Conf., May 1969, pp. 581586.
    19. 19)
      • 19. Zimmermann, R., Fichtner, W.: ‘Low-power logic styles: CMOS versus pass-transistor logic’, IEEE J. Solid-State Circuits, 1997, 32, (7), pp. 112 (doi: 10.1109/4.597298).
    20. 20)
      • 20. Law, C.F., Rofail, S.S., Yeo, K.S.: ‘A low power 16 × 16-b parallel multiplier utilizing pass-transistor logic’, IEEE J. Solid-State Circuits, 1999, 34, (10), pp. 13951399 (doi: 10.1109/4.792613).
    21. 21)
      • 21. Weste, N.H.E., Harris, D., Banerjee, A.: ‘CMOS VLSI design: a circuits and systems perspective’ (Pearson Education, 2005, 3rd edn.), pp. 263275.
    22. 22)
      • 22. (Steve) Kang, S.-M., Leblebici, Y.: ‘CMOS digital integrated circuits: analysis and design’ (Tata McGraw-Hill Publishing Company Limited, New Delhi, 2003, 3rd edn.), pp. 397400.
    23. 23)
      • 23. Ghosh, D., Sural, S., Nandy, S.K.: ‘A 600 MHz half-bit level pipelined multiplier macrocell’. Seven Int. Conf. on VLSI Design, Calcutta, India, January 1994, pp. 95100.
    24. 24)
      • 24. Saha, A., Pal, D., Chandra, M., Goswami, M.K.: ‘Novel high speed MCML 8-bit by 8-bit multiplier’. IEEE Int. Conf. on Devices and Communications (ICDeCom-11), BIT, Mesra, India, 24–25 February 2011, pp. 15.
    25. 25)
      • 25. Ramanathan, P., Vanathi, P.T., Agarwal, S.: ‘High speed multiplier design using decomposition logic’, Serb. J. Electr. Eng., 2009, 6, (1), pp. 3342 (doi: 10.2298/SJEE0901033R).
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