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access icon free A 0.38 V near/sub-V T digitally controlled low-dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process

© The Institution of Engineering and Technology
Received 14/06/2011, Accepted 10/10/2012, Revised 18/09/2012, Published

This study describes a 0.38 V digitally controlled low-dropout (LDO) voltage regulator enabling dynamic voltage scaling (DVS) for near/sub-threshold applications. For operating at an ultra-low supply voltage, analogue components are replaced in conventional LDOs with digital counterparts. Especially, a digital reference control that is based on a replica circuit is proposed to improve power supply noise rejection and line regulation of the LDO. The proposed LDO has been designed in a 90 nm regular V T complementary metal oxide semiconductor technology. The LDO can regulate the output voltage from 0.12 to 0.32 V with a supply voltage of 0.38 V. Furthermore, it reaches the current efficiency of 99.3% and the power efficiency of 83.6%, respectively, at a load current of 1 mA. The digitally controllable DVS with 3 mV resolution is achieved.

Inspec keywords: voltage regulators; CMOS integrated circuits; power supply circuits

Other keywords: DVS; voltage 0.38 V; near-sub-threshold application; near-sub-VT digitally controlled low-dropout voltage regulator; ultra-low power supply noise rejection; efficiency 83.6 percent; voltage 0.12 V to 0.32 V; size 90 nm; digital reference control; dynamic voltage scaling; current 1 mA; voltage 3 mV; efficiency 99.3 percent; regular VT complementary metal oxide semiconductor technology; line regulation; LDO

Subjects: Power electronics, supply and supervisory circuits; CMOS integrated circuits

References

    1. 1)
      • 22. Yang, C.-Y., Dehng, G.-K., Hsu, J.-M., Liu, S.-I.: ‘New dynamic flip-flops for high-speed dual-modulus prescaler’, IEEE J. Solid-State Circuits, 1998, 33, (10), pp. 1568–1571 (doi: 10.1109/4.720406).
    2. 2)
      • 5. Wang, A., Chandrakasan, A.: ‘A 180-mV subthreshold FFT processor using a minimum energy design methodology’, IEEE J. Solid-State Circuits, 2005, 40, (1), pp. 310–319 (doi: 10.1109/JSSC.2004.837945).
    3. 3)
      • 28. Hazucha, P., Moon, S.-T., Schrom, G., et al: ‘High voltage tolerant linear regulator with fast digital control for biasing of integrated DC-DC converters’, IEEE J. Solid-State Circuits, 2007, 42, (1), pp. 66–73 (doi: 10.1109/JSSC.2006.885060).
    4. 4)
      • 25. Zhan, C., Ki, W.-H.: ‘Output-capacitor-free adaptively biased low-dropout regulator for system-on-chips’, IEEE Trans. Circuits Syst. I, 2010, 57, (5), pp. 1017–1028 (doi: 10.1109/TCSI.2010.2046204).
    5. 5)
      • 1. Chatterjee, S., Tsividis, Y., Kinget, P.: ‘0.5-V analog circuit techniques and their application in OTA and filter design’, IEEE J. Solid-State Circuits, 2005, 40, (12), pp. 2373–2387 (doi: 10.1109/JSSC.2005.856280).
    6. 6)
      • 30. Or, P.Y., Leung, K.N.: ‘An output-capacitorless low-dropout regulator with direct voltage-spike detection’, IEEE J. Solid-State Circuits, 2010, 45, (2), pp. 458–466 (doi: 10.1109/JSSC.2009.2034805).
    7. 7)
      • 21. Alon, E., Stojanovic, V., Horowitz, M.: ‘Circuits and techniques for high-resolution measurement of on-chip power supply noise’, IEEE J. Solid-State Circuits, 2005, 40, (4), pp. 820–828 (doi: 10.1109/JSSC.2004.842853).
    8. 8)
      • 11. Fujiyoshi, T., Shiratake, S., Nomura, S., et al: ‘A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic voltage/frequency scaling’, IEEE J. Solid-State Circuits, 2006, 41, (1), pp. 54–62 (doi: 10.1109/JSSC.2005.859337).
    9. 9)
      • 23. Teel, J.C.: ‘Understanding power supply ripple rejection in linear regulators’, Analog Appl. J., 2005, pp. 8–11.
    10. 10)
      • 13. Hwang, Y.-S., Lin, M.-S., Hwang, B.-H., Chen, J.-J.: ‘A 0.35 μm CMOS sub-1V low-quiescent-current low-dropout regulator’. Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), November 2008, pp. 153–156.
    11. 11)
      • 18. Fayomi, C., Wirth, G., Achigui, H., Matsuzawa, A.: ‘Sub 1 V CMOS bandgap reference design techniques: a survey’, Analog Integr. Circuits Signal Process., 2010, 62, pp. 141–157 (doi: 10.1007/s10470-009-9352-4).
    12. 12)
      • 8. Keane, J., Eom, H., Kim, T.-H., Sapatnekar, S., Kim, C.: ‘Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing’. Proc. IEEE/ACM Design Automation Conf. (DAC), July 2006, pp. 425–428.
    13. 13)
      • 17. Zheng, C., Ma, D.: ‘Design of monolithic CMOS LDO regulator with D2 coupling and adaptive transmission control for adaptive wireless powered bio-implants’, IEEE Trans. Circuits Syst. I, 2011, 58, (10), pp. 2377–2387 (doi: 10.1109/TCSI.2011.2123650).
    14. 14)
      • 24. Heng, S., Pham, C.-K.: ‘A low-power high-PSRR low-dropout regulator with bulk-gate controlled circuit’, IEEE Trans. Circuits Syst. II, 2010, 57, (4), pp. 245–249 (doi: 10.1109/TCSII.2010.2043390).
    15. 15)
      • 19. Mansuri, M., Yang, C.-K.: ‘A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation’, IEEE J. Solid-State Circuits, 2003, 38, (11), pp. 1804–1812 (doi: 10.1109/JSSC.2003.818300).
    16. 16)
      • 15. Kim, Y., Li, P.: ‘An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration’. Proc. IEEE Int. Symp. Quality Electronic Design (ISQED), March 2012, pp. 151–158.
    17. 17)
      • 26. Hazucha, P., Karnik, T., Bloechel, B., Parsons, C., Finan, D., Borkar, S.: ‘Area-efficient linear regulator with ultra-fast load regulation’, IEEE J. Solid-State Circuits, 2005, 40, (4), pp. 933–940 (doi: 10.1109/JSSC.2004.842831).
    18. 18)
      • 7. Luo, S.-C., Chiou, L.-Y.: ‘A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing’, IEEE Trans. Circuits Syst. II, 2010, 57, (6), pp. 440–445 (doi: 10.1109/TCSII.2010.2048360).
    19. 19)
      • 29. Lam, Y.-H., Ki, W.-H.: ‘A 0.9 V 0.35 μm adaptively biased CMOS LDO regulator with fast transient response’. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, February 2008, pp. 442–626.
    20. 20)
      • 6. Kaul, H., Anders, M., Mathew, S., et al: ‘A 320 mV 56 μW 411 GOPS/watt ultra-low voltage motion estimation accelerator in 65 nm CMOS’, IEEE J. Solid-State Circuits, 2009, 44, (1), pp. 107–114 (doi: 10.1109/JSSC.2008.2007164).
    21. 21)
      • 20. Wu, T., Mayaram, K., Moon, U.-K.: ‘An on-chip calibration technique for reducing supply voltage sensitivity in ring oscillators’, IEEE J. Solid-State Circuits, 2007, 42, (4), pp. 775–783 (doi: 10.1109/JSSC.2007.892194).
    22. 22)
      • 9. Tajalli, A., Leblebici, Y.: ‘Leakage current reduction using subthreshold source-coupled logic’, IEEE Trans. Circuits Syst. II, 2009, 56, (5), pp. 374–378 (doi: 10.1109/TCSII.2009.2019167).
    23. 23)
      • 14. Guo, J., Leung, K.N.: ‘A 6-μW chip-area-efficient output-capacitorless LDO in 90-nm CMOS technology’, IEEE J. Solid-State Circuits, 2010, 45, (9), pp. 1896–1905 (doi: 10.1109/JSSC.2010.2053859).
    24. 24)
      • 27. Huang, W.-J., Liu, S.-I.: ‘Sub-1V capacitor-free low-dropout regulator’, IET Electron. Lett., 2006, 42, (24), pp. 1395–1396 (doi: 10.1049/el:20062871).
    25. 25)
      • 2. Gambini, S., Rabaey, J.: ‘Low-power successive approximation converter with 0.5 V supply in 90 nm CMOS’, IEEE J. Solid-State Circuits, 2007, 42, (11), pp. 2348–2356 (doi: 10.1109/JSSC.2007.906210).
    26. 26)
      • 4. Okuma, Y., Ishida, K., Ryu, Y., et al: ‘0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65 nm CMOS’. Proc. IEEE Custom Integrated Circuits Conf. (CICC), September 2010, pp. 1–4.
    27. 27)
      • 10. Gupta, S., Raychowdhury, A., Roy, K.: ‘Digital computation in subthreshold region for ultralow-power operation: a device-circuit-architecture codesign perspective’, Proc. IEEE, 2010, 98, (2), pp. 160–190 (doi: 10.1109/JPROC.2009.2035060).
    28. 28)
      • 16. Zheng, C., Ma, D.: ‘Design of monolithic low dropout regulator for wireless powered brain cortical implants using a line ripple rejection technique’, IEEE Trans. Circuits Syst. II, 2010, 57, (9), pp. 686–690 (doi: 10.1109/TCSII.2010.2056090).
    29. 29)
      • 3. Lo, Y.-L., Yang, W.-B., Chao, T.-S., Cheng, K.-H.: ‘Designing an ultralow-voltage phase-locked loop using a bulk-driven technique’, IEEE Trans. Circuits Syst. II, 2009, 56, (5), pp. 339–343 (doi: 10.1109/TCSII.2009.2019160).
    30. 30)
      • 12. Howard, J., Dighe, S., Vangal, S., et al: ‘A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling’, IEEE J. Solid-State Circuits, 2011, 46, (1), pp. 173–183 (doi: 10.1109/JSSC.2010.2079450).
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