access icon free High-loop-delay sixth-order bandpass continuous-time sigma–delta modulators

This study focuses on the design of high-loop-delay modulators for parallel sigma–delta conversion. Parallel converters, allowing a global low oversampling ratio, consist of several bandpass modulators with adjacent central frequencies. To ensure the global performance, the noise transfer function (NTF) of each modulator must be adjusted regarding its central frequency. In this thematic a new topology of sixth-order modulators based on weighted-feedforward techniques is developed. This topology offers an adequate control of the NTF at each central frequency by simple means. Additive signal paths are moreover proposed to obtain an auto-filtering signal transfer function. An optimisation method is also developed to calculate the optimised coefficients of the modulators at different central frequencies. The main concerns are improving the stability and reducing the sensitivity of the continuous-time circuit to analogue imperfections. This is essential for parallel conversion since, in each channel, the modulator works at a central frequency which differs from the fourth of the sampling frequency. The performance of the optimised modulator is compared with its discrete-time counterpart with good argument.

Inspec keywords: sigma-delta modulation; filtering theory

Other keywords: sixth-order bandpass continuous-time sigma-delta modulator; auto-filtering signal transfer function; optimisation method; continuous-time circuit; high-loop-delay modulator; bandpass modulator; parallel converter; noise transfer function; parallel sigma-delta conversion; additive signal path; parallel conversion; weighted-feedforward technique

Subjects: A/D and D/A convertors; A/D and D/A convertors; Filtering methods in signal processing

References

    1. 1)
      • 10. Maghari, N., Temes, G.C., Moon, U.: ‘Single-loop ΣΔ modulator with extended dynamic range’, IET Electron. Lett., 2008, 44, pp. 14521453 (doi: 10.1049/el:20082717).
    2. 2)
      • 17. Desvergne, M., Bernier, C., Vincent, P., Deval, Y., Begueret, J.B.: ‘Intermediate frequency lamb wave resonators and filters for RF receiver architectures’. IEEE Int. Conf. on Electronics Circuits and Systems, December 2006, vol. 10, no. 13, pp. 10451048.
    3. 3)
      • 16. Banyasz, C.S., Keviczky, L.: ‘A new gap metric for robustness measure and regulator design’. Proc. 17th IEEE Mediterranean Conf. on Control and Automation (MED '09), Thessaloniki, Greece, June 2009.
    4. 4)
      • 4. Reddy, K., Pavan, S.: ‘Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter’, IEEE Trans. Circuits Syst. I, 2007, 54, (10), pp. 21842194 (doi: 10.1109/TCSI.2007.905648).
    5. 5)
      • 7. Yahia, A., Benabes, P.: ‘Bandpass sigma-delta modulators synthesis with high loop delay’. IEEE Int. Conf. on Circuits and Systems, May 2001, vol. 1, pp. 344347.
    6. 6)
      • 5. Oliaei, O.: ‘Design of continuous-time sigma-delta modulators with arbitrary feedback waveform’, IEEE Trans. Circuits Syst. II, Analog Digital Signal Process., 2003, 50, (8), pp. 437444 (doi: 10.1109/TCSII.2003.814806).
    7. 7)
      • 13. Ashry, A., Aboushady, H.: ‘Simple architecture for subsampling LC-based ΣΔ modulators’, IET Electron. Lett., 2010, 46, pp. 12631264 (doi: 10.1049/el.2010.1567).
    8. 8)
      • 9. Javidan, M., Benabes, P.: ‘A new method to synthesize and optimize band-pass delta-sigma modulators’. IEEE Int. Conf. Circuits and Systems and TAISA Conf., June 2008, pp. 197200.
    9. 9)
      • 15. Rakulijic, N., Galton, I.: ‘Tree-structured DEM DACs with arbitrary numbers of levels’, IEEE Trans. Circuits Syst. I, 2009, 57, pp. 313322 (doi: 10.1109/TCSI.2009.2023931).
    10. 10)
      • 1. Eshraghi, A., Fiez, T.S.: ‘A comparative analysis of parallel delta-sigma ADC architectures’, IEEE Trans. Circuits Syst. I, 2004, 51, (3), pp. 450458 (doi: 10.1109/TCSI.2004.823663).
    11. 11)
      • 2. Benabes, P., Beydoun, A., Oksman, J.: ‘Extended frequency-band-decomposition sigma-delta A/D converter’, SpringerLink J. Analog Integr. Circuits Signal Process., 2009, 61, (1) (doi: 10.1007/s10470-008-9274-6).
    12. 12)
      • 11. Van Engelen, J.A.E.P., J Van de Plassche, R., Stikvoort, E., Venes, A.G.: ‘A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF’, IEEE J. Solid State Circuits, 1999, 34, (12), pp. 17531764 (doi: 10.1109/4.808900).
    13. 13)
      • 8. Hamoui, A., Martin, K.W.: ‘High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications’, IEEE Trans. Circuits Syst. I, 2004, 51, pp. 7285 (doi: 10.1109/TCSI.2003.821291).
    14. 14)
      • 18. Javidan, M., Benabes, P.: ‘Design of electronic control circuit of piezo-electric resonators for modulator loop in AMS Bi-CMOS 0.35 μm’. IEEE Int. Conf. on Circuits and Systems and TAISA Conf., June 2010, pp. 4548.
    15. 15)
      • 19. http://www.artemos.eu.
    16. 16)
      • 3. Candy, C., Times, G.C.: ‘Oversampling delta-sigma data converters: theory, design, and simulations’ (Handbook, Wiley-IEEE Press, 1991).
    17. 17)
      • 12. Yu, R., Xu, Y.: ‘Band-pass sigma-delta modulator employing SAW resonator as loop filter’, IEEE Trans. Circuits Syst. I, 2007, 54, (4), pp. 723735 (doi: 10.1109/TCSI.2007.890615).
    18. 18)
      • 14. Cherry, J.A., Snelgrove, W.M.: ‘Excess loop delay in continuous-time delta-sigma modulators’, IEEE Trans. Circuits Syst. II, 1999, 46, (4), pp. 376389 (doi: 10.1109/82.755409).
    19. 19)
      • 6. Fischer, G., Davis, A.J.: ‘Alternative topologies for sigma-delta modulators – a comparative study’, IEEE Trans. Circuits Syst. II, Analog Digital Signal Process., 1997, 44, (10), pp. 789797 (doi: 10.1109/82.633433).
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