References

• 1. 1)
     • Jamaa, M.H.B., Moselund, K.E., Atienza, D.: `Fault-tolerant multi-level logic decoder for nanoscale cross memory arrays', Proc. IEEE Int. Conf. on Computer-Aided Design (ICCAD), 2007, p. 765–772.
  2. 2)
     • A. Conte , G. Lo Giudice , G. Palumbo , A. Signorello . A high-performance very low-voltage current sense amplifier for nonvolatile memories. IEEE J. Solid-State Circuits , 2 , 507 - 514
  3. 3)
     • L. Jacunski , S. Soyle , D. Jallice , N. Haddad , T. Scott . SEU immunity: the effects of scaling on the peripheral circuits of SRAMs. IEEE Trans. Nucl. Sci. , 6 , 2272 - 2276
  4. 4)
     • Alowersson, J.: `A CMOS circuit technique for high-speed RAMs', Proc. Sixth Annual IEEE Int. ASIC Conf. and Exhibit, 1993, p. 243–246.
  5. 5)
     • Wang, F., Agrawal, V.D.: `Single event upset: an embedded tutorial', Proc. IEEE 21st Int. Conf. on VLSI Design, VLSID 2008, 4–8 January 2008, p. 429–434.
  6. 6)
     • Turi, M.A., Delgado-Frias, J.G., Jha, N.K.: `Low-power FinFET design schemes for NOR address decoders', Proc. IEEE Int. Symp. on VLSI Design, Automation and Test, VLSI-DAT, April 2010, p. 74–77.
  7. 7)
     • P.T. McDonald , W.J. Stapor , A.B. Campbell , L.W. Massengill . Non-random single event upset trends. IEEE Trans. Nucl. Sci. , 6 , 2324 - 2329
  8. 8)
     • Rachlin, E., Savage, J.E.: `Nanowire addressing in the face of uncertainty', Proc. Emerging VLSI Technologies and Architectures (ISVLSI’06), 2006, p. 1–6.
  9. 9)
     • W. Zhao , Y. Cao . Predictive technology model for nano-CMOS design exploration. ACM J. Emerg. Technol. Comput. Syst. , 1 , 1 - 17
  10. 10)
      • E.H. Neto , G. Wirth , F.L. Kastensmidt . Mitigating soft errors in SRAM address decoders using built-in current sensors. J. Electron. Test. , 425 - 437
  11. 11)
      • D.J. Frank , R.H. Dennard , E. Nowak , P.M. Solomon , Y. Taur , H.P. Wong . Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE , 3 , 259 - 288
  12. 12)
      • J.J. Barnes , A.L. De Jesus , D. Novosel . Circuit techniques for a 25 ns 16 K×1 SRAM using address-transition detection. IEEE J. Solid-State Circuits , 4 , 455 - 461
  13. 13)
      • Synopsys HSPICE User Manual, 2010.
  14. 14)
      • Kim, Y.B., Kim, Y.B., Lombardi, F.: `New SRAM cell design for low power and high reliability using 32 nm independent gate FinFET technology', Proc. IEEE Int. Workshop on Design and Test of Nano Devices, Circuits and Systems, 2008, p. 25–28.