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Process variations aware area efficient negative bit-line voltage scheme for improving write ability of SRAM in nanometer technologies

Process variations aware area efficient negative bit-line voltage scheme for improving write ability of SRAM in nanometer technologies

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The increased device variations, lower supply voltages have enforced the usage of write-assist circuits in static random access memory (SRAMs) in the nano-complementary metal oxide semiconductor (CMOS) regime. Negative bit-line scheme during write has been found one of the most promising write-assist solutions. A new low power, negative bit-line scheme is presented. The presented negative bit-line technique can be used to improve the write ability of 6 T single-port (SP) as well as 8 T dual-port (DP) and other multiport SRAM cells. Negative voltage is generated on-chip using capacitive coupling. Only the bit-line on which a ‘0’ is to be written is taken negative during write operation. The proposed circuit design topology does not affect the read operation for bit-interleaved architectures enabling high-speed operation. Simulation results and comparative study of the present scheme with state-of-the art conventional schemes proposed in the literature for 45 nm CMOS technology show that the proposed scheme is superior in terms of process-variations impact, area overhead, timings and dynamic power consumption.

References

    1. 1)
      • Chang, L., Fried, D.M., Hergenrother, J.: `Stable SRAM cell design for the 32 nm node and beyond', Symp. VLSI Circuits Digital Technical Papers, June 2005, p. 128–129.
    2. 2)
      • Nii, K., Tenoh, Y., Yoshizawa, T.: `A 90 nm low power 32 Kbyte embedded SRAM with gate leakage suppression circuit for mobile applications', Symp. VLSI Circuits Digital Technical Papers, June 2003, p. 247–250.
    3. 3)
    4. 4)
    5. 5)
      • K. Zhang , U. Bhattacharya , Z. Chen . A 3-GHz 70 Mb SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply. ISSCC Dig. Tech. Papers , 474 - 475
    6. 6)
    7. 7)
    8. 8)
    9. 9)
      • Shibata, N., Douseki, T., Kurita, S.: `Bitline-overdriven writing circuitry for ultralow-voltage MTCMOS SRAMs', Proc. IEICE Electronics Society Conf., September 2003, p. 100, vol. C-12–25.
    10. 10)
      • Douseki, T., Shibata, N., Yamada, J.: `A 0.5–1 V MTCMOS/SIMOX SRAM macro with multi-V memory cells', Proc. IEEE Int. SOI Conf., October 2000, p. 24.
    11. 11)
      • N. Shibata , H. Inokawa , K. Tokunaga , S. Ohta . Megabit-class size configurable 250-MHz SRAM macrocells with a squashed-memory-cell architecture. IEICE Trans. Electron. , 1 , 94 - 104
    12. 12)
    13. 13)
    14. 14)
    15. 15)
      • N. Shibata , Y. Goto , S. Date . High-performance memory macrocells with row and column sliceable architecture. IEICE Trans. Electron. , 11 , 1641 - 1648
    16. 16)
    17. 17)
      • V. Chandra , C. Pietrzyk , R. Aitken . On the efficacy of write-assist techniques in low voltage nanoscale SRAMs.
    18. 18)
      • N. Shibata . Current sense amplifiers for low-voltage memories. IEICE Trans. Electron. , 8 , 1120 - 1130
    19. 19)
    20. 20)
      • Yamaoka, M., Osada, K., Ishibashi, K.: `0.4-V logic library friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme', Symp. VLSI Circuits Digital Technical Papers, June 2002, p. 170–173.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2011.0036
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