Stability of hydrogenated polymorphous silicon thin-film transistors under DC electrical stress

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Stability of hydrogenated polymorphous silicon thin-film transistors under DC electrical stress

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The authors fabricated bottom-gate (BG) back-channel etched (BCE) thin-film transistors with hydrogenated polymorphous silicon (pm-Si:H) as the channel material. This material is obtained using the same low-cost plasma-enhanced chemical vapour deposition (PECVD) techniques as amorphous silicon. The authors first show the improvement of the threshold voltage stability of pm-Si:H TFTs under bias stress compared to a-Si:H counterparts. Then, pm-Si:H TFTs degradation is investigated under different gate bias stress conditions. It has been found that the degradation mechanisms are dependent on the gate stress conditions involving state creation in the channel material and charge trapping at the channel/gate SiNx interface.

Inspec keywords: elemental semiconductors; stability; hydrogen; stress effects; thin film transistors; etching; amorphous semiconductors; plasma CVD; silicon compounds; silicon

Other keywords: low-cost plasma-enhanced chemical vapour deposition techniques; threshold voltage stability; PECVD; gate bias stress conditions; hydrogenated polymorphous silicon thin-film transistors; degradation mechanisms; DC electrical stress; channel material; charge trapping; channel-gate interface; BG-BCE thin-film transistors; Si:H-SiNx; bottom-gate back-channel etched thin-film transistors

Subjects: Other field effect devices

References

    1. 1)
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    3. 3)
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    5. 5)
    6. 6)
      • Dosev, D.: `Fabrication, characterisation and modelling of nanocristalline thin-film transistors obtained by hot-wire chemical vapour deposition', 2003, PhD, Universitat politècnica de Catalunya (Barcelona).
    7. 7)
    8. 8)
    9. 9)
    10. 10)
    11. 11)
    12. 12)
    13. 13)
      • Templier, F., Oudwan, M., Sermet, F., Demars, P.: `Mechanisms of threshold voltage drift in nanocrystalline thin-film transistors for active-matrix displays', Proc. Third Int. ITC Conf., 2007, Roma, Italy.
    14. 14)
    15. 15)
    16. 16)
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