5.6 Gb/s receiver with electrical overstress protection for GDDR in a 45 nm CMOS

Author(s): T. Sümesağlam ; R. Song ; G.R. Murray ; A. Guerra
DOI: 10.1049/iet-cds.2010.0212

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Author(s): T. Sümesağlam ¹ ; R. Song ² ; G.R. Murray ¹ ; A. Guerra ²
- Affiliations: 1: Intel Corporation, Folsom, USA
  2: Intel Corporation, Santa Clara, USA
Source: Volume 5, Issue 4, July 2011, p. 329 – 333
DOI: 10.1049/iet-cds.2010.0212 , Print ISSN 1751-858X, Online ISSN 1751-8598

A receiver circuit with built-in electrical overstress protection for a graphics double data rate, version 5 (GDDR5) interface is proposed. The new circuit in a fully functional memory controller system is fabricated in a 45 nm CMOS process using only native thin-gate transistors. The receiver's functionality and performance are experimentally verified at 5.6 Gb/s with 20 ps set-up/hold and 54 mVpp voltage uncertainty with better than 10⁻¹² bit error rate (BER).

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5.6 Gb/s receiver with electrical overstress protection for GDDR in a 45 nm CMOS

5.6 Gb/s receiver with electrical overstress protection for GDDR in a 45 nm CMOS

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