5.6 Gb/s receiver with electrical overstress protection for GDDR in a 45 nm CMOS

5.6 Gb/s receiver with electrical overstress protection for GDDR in a 45 nm CMOS

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A receiver circuit with built-in electrical overstress protection for a graphics double data rate, version 5 (GDDR5) interface is proposed. The new circuit in a fully functional memory controller system is fabricated in a 45 nm CMOS process using only native thin-gate transistors. The receiver's functionality and performance are experimentally verified at 5.6 Gb/s with 20 ps set-up/hold and 54 mVpp voltage uncertainty with better than 10−12 bit error rate (BER).


    1. 1)
    2. 2)
    3. 3)
      • JEDEC Standard JESD8-20A, POD15–1.5 V Pseudo Open Drain I/O.
    4. 4)
    5. 5)
      • Serneels, B., Piessens, T., Steyaert, M., Dehaene, W.: `A high-voltage output driver in a standard 2.5 V 0.25 um CMOS technology', IEEE Proc. ISSCC, 2004, p. 146–147.
    6. 6)
      • Kim, M.-J., Icking, H., Gossner, H., Lee, T.H.: `High-voltage-tolerant I/O circuit design for USB 2.0-compliant applications', IEEE Proc. CICC, 2007, p. 491–494.
    7. 7)
    8. 8)
    9. 9)
    10. 10)
    11. 11)
    12. 12)
    13. 13)
      • ‘PCI Express base specification revision 2.1’, 2009.

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