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5.6 Gb/s receiver with electrical overstress protection for GDDR in a 45 nm CMOS

5.6 Gb/s receiver with electrical overstress protection for GDDR in a 45 nm CMOS

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A receiver circuit with built-in electrical overstress protection for a graphics double data rate, version 5 (GDDR5) interface is proposed. The new circuit in a fully functional memory controller system is fabricated in a 45 nm CMOS process using only native thin-gate transistors. The receiver's functionality and performance are experimentally verified at 5.6 Gb/s with 20 ps set-up/hold and 54 mVpp voltage uncertainty with better than 10−12 bit error rate (BER).

References

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