Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling

Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Owing to increase in parametric variations with technology scaling, accurate estimation of bit-cell failure probability in nano-scale static random access memory (SRAM) has become an extremely challenging task. In this study, the authors propose a method to detect the SRAM bit-cell failure, named ‘critical point sampling’. Using this technique, read and hold failure probability of an SRAM bit-cell can be efficiently estimated in a simulation-based way. Simulation results show that our estimation method provides high accuracy, while being ∼50× faster in computational speed compared to transient Monte-Carlo simulation. The method can be applied to optimise SRAM design for better yield and contributes significantly in reducing the overall design time.


    1. 1)
      • S. Mukhopadhyay , H. Mahmoodi , K. Roy . Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. Comput. Aided Des. , 12 , 1859 - 1880
    2. 2)
      • A.J. Bhavnagarwala , X. Tang , J.D. Meindl . The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J. Solid State Circuits , 4 , 658 - 665
    3. 3)
      • X. Tang , V. De , J.D. Meindl . Intrinsic MOSFET parameter fluctuations due to random dopant placement. IEEE Trans. VLSI Syst. , 369 - 376
    4. 4)
      • Joshi, R.V., Mukhopadhyay, S., Plass, D.W., Chan, Y.H., Chuang, C.-Te., Devgan, A.: `Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell', ESSCIRC Dig. Tech. Papers, 2004, p. 211–214.
    5. 5)
      • Chang, I., Kang, K., Kim, C.H., Mukhopadhyay, S., Roy, K.: `Fast and accurate estimation of read failure probability using critical point sampling in nano-scaled SRAM', CICC Dig. Tech. Papers, 2005, p. 439–442.
    6. 6)
      • Kanj, R., Joshi, R., Nassif, S.: `Mixture importance sampling and its application to the analysis of SRAM design in the presence of rare failure events', DAC, 2006.
    7. 7)
    8. 8)
    9. 9)
      • Y. Taur , T.H. Ning . (1998) Fundamentals of modern VLSI devices.
    10. 10)
    11. 11)
      • J.M. Rabaey , A. Chandrakasan , B. Nikolic . (2003) Digital integrated circuit.
    12. 12)
      • A. Papoulis . (1991) Probability, random variables and stochastic processes.
    13. 13)
      • T.W. Anderson , D.A. Darling . Asymptotic theory of certain “goodness of fit” criteria based on stochastic processes. Ann. Math. Stat. , 2 , 193 - 212

Related content

This is a required field
Please enter a valid email address