© The Institution of Engineering and Technology
This study proposes a gradient-free approach to integrated circuit sizing that takes into account the statistical variations of device parameters and ranges of operating conditions. A novel gradient-free algorithm for solving the worst-case performance problem is proposed. The proposed algorithm produces corners that are used in the optimisation loop of the circuit sizing process. The set of corners is dynamically updated during circuit sizing. The number of corners is kept low by considering only corners that are sufficiently unique. The final result is a circuit exhibiting the specified parametric yield. The proposed approach was tested on several circuits and the results were verified with Monte–Carlo analysis and worst-case distances. All resulting circuits were obtained in up to 12 h on a single processor and exhibited the specified yield. The method can easily be parallelised to an extent that can bring the runtime of the method in the range of an hour or less.
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http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2010.0094
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