Linearity improvement of open-loop NMOS source-follower sample and hold circuits

Access Full Text

Linearity improvement of open-loop NMOS source-follower sample and hold circuits

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

A new open-loop sample and hold (S/H) circuit is proposed for high-speed sampled data applications. The open-loop S/H circuit uses the source-follower configuration, for its high speed, low power consumption, small area and low circuit complexity. In order to achieve high linearity, a body effect cancellation technique is proposed which is based on proper modulation of the bias current of the source-follower transistor. Simulated by HSPICE with a standard BSIM3v3 0.18 µm CMOS technology, the pseudo-differential open-loop S/H achieves over 76 dB spurious free dynamic range (SFDR) for a 1.6 Vppd output at 200 MHz sampling frequency. The S/H dissipates 12.5 mW power from a 1.8 V supply.

Inspec keywords: MOSFET; circuit complexity; CMOS analogue integrated circuits; sample and hold circuits

Other keywords: voltage 1.8 V; high speed low power consumption; power 12.5 mW; source-follower transistor; BSIM3v3 CMOS technology; frequency 200 MHz; voltage 1.6 V; body effect cancellation technique; spurious free dynamic range; low circuit complexity; size 0.18 mum; pseudo-differential open-loop S/H circuit; HSPICE; open-loop NMOS source-follower sample and hold circuits

Subjects: CMOS integrated circuits; Other analogue circuits; Insulated gate field effect transistors

References

    1. 1)
    2. 2)
      • Shahramian, S., Voinigescu, S.P., Carusone, A.C.: `A 30-GS/sec track and hold amplifier in 0.13-µm CMOS technology', 2006 IEEE Custom Integrated Circuits Conf., September 2006, p. 493–496.
    3. 3)
    4. 4)
      • Chen, G., Luo, Y., Drake, A., Zhou, K.: `A 5-bit 10 GS/s 65 nm flash ADC with feedthrough cancellation track-and-hold circuit', 2009 IEEE Int. Midwest Symp. on Circuits and Systems, 2009, August 2009, p. 423–426, MWSCAS 2009.
    5. 5)
      • Keshavarzi, A., Ma, S., Narendra, S.: `Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs', 2001 IEEE Int. Symp. on Low Power Electronics, August 2001, p. 207–212.
    6. 6)
    7. 7)
      • W.M.C. Sansen . (2006) Analog design essentials.
    8. 8)
      • Hadidi, K., Sasaki, M., Watanabe, T., Muramatsu, D., Matsumoto, T.: `An open-loop full CMOS 103 MHz-61 dB THD S/H circuit', 1998 IEEE Custom Integrated Circuits Conf., May 1998, p. 381–383.
    9. 9)
      • Hadidi, K., Muramatsu, D., Oue, T., Matsumoto, T.: `A 500 MS/sec-54 dB THD S/H circuit in a 0.5 µm CMOS process', Proc. 25th European Solid-State Circuits Conf., September 1999, p. 158–161.
    10. 10)
      • Jiang, X., Wang, Z., Chang, M.F.: `A 2GS/s 6 b ADC in 0.18 µm CMOS', IEEE Int. Solid-State Circuits Conf., February 2003, XLVI, p. 322–323.
    11. 11)
      • B. Razavi . (2002) Design of analog CMOS integrated circuits.
    12. 12)
      • Hsu, C.-C., Huang, F.-C., Shih, C.-Y.: `An 11 b 800 MS/s time-interleaved ADC with digital background calibration', IEEE Int. Solid-State Circuits Conf. on Digest Technical Papers, February 2007, p. 464–465.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2009.0312
Loading

Related content

content/journals/10.1049/iet-cds.2009.0312
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading