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A 1.5 GHz phase-locked loop with leakage current suppression in 65 nm CMOS

A 1.5 GHz phase-locked loop with leakage current suppression in 65 nm CMOS

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In the nanoscale CMOS process, the problem of leakage current causes the performance of the analog circuits to degrade. The leakage current of a loop filter, which is realised by MOS capacitors, significantly degrades the jitter performance of a phase-locked loop. A leakage suppression circuit is presented by using a combination of switchable varactors and current sources to compensate the leakage of MOS capacitors in a loop filter. This PLL has been fabricated in a 65 nm CMOS process and the core area is 0.4×0.5 mm2. With the leakage suppression circuit, the peak-to-peak jitter and the rms jitter are 43 and 5.36 ps, respectively. The power is 17 mW for a 1.2 V supply.

Inspec keywords: UHF integrated circuits; jitter; phase locked loops; leakage currents; CMOS analogue integrated circuits; UHF filters; varactors; MOS capacitors

Other keywords: loop filter; frequency 1.5 GHz; size 65 nm; leakage current suppression; analog circuits; leakage suppression circuit; MOS capacitors; jitter; voltage 1.2 V; nanoscale CMOS process; switchable varactors; power 17 mW; phase-locked loop; peak-to-peak jitter

Subjects: Modulators, demodulators, discriminators and mixers; Microwave integrated circuits; CMOS integrated circuits; Filters and other networks; Capacitors

References

    1. 1)
      • C.F. Liang , S.H. Chen , S.I. Liu . A digital calibration technique for CPs in phase-locked systems. IEEE J. Solid-State Circuits , 390 - 398
    2. 2)
      • G.A. Rincon-Mora . Active capacitor multiplier in Miller-compensated circuits. IEEE J. Solid-State Circuits , 26 - 32
    3. 3)
      • T.C. Lee , B. Razavi . A stabilization technique for phase-locked frequency synthesizers. IEEE J. Solid-State Circuits , 888 - 894
    4. 4)
      • A. Abdollahi , F. Fallah , M. Pedram . Leakage current reduction in CMOS VLSI circuits by input vector control. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 2 , 140 - 153
    5. 5)
      • Foley, C.: `Characterizing metastability', Advanced Research in Asynchronous Circuits and Systems, Second Int. Symp., March 1996, p. 175–184.
    6. 6)
      • Hung, C.C., Liu, S.I.: `A leakage-suppression technique for phase-locked systems in 65 nm CMOS technology', Int. Solid-State Circuits Conf. (ISSCC), February 2009, p. 400–401.
    7. 7)
      • F. Gardner . Charge-pump phase-lock loops. IEEE Trans. Commun. , 1849 - 1858
    8. 8)
      • W.S.T. Yan , H.C. Luong . A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator. IEEE Trans. Circuits Syst. II , 216 - 221
    9. 9)
      • Holzer, R.: `A 1V CMOS PLL designed in high-leakage CMOS process operating at 10–700 MHz', IEEE Int. Solid-State Circuits Conf., February 2002, p. 272–273.
    10. 10)
      • C.N. Chuang , S.I. Liu . A 1 V phase locked loop with leakage compensation in 0.13 µm CMOS technology. IEICE Trans. Electron. , 295 - 299
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