Single poly-EEPROM with stacked MIM and n-well capacitor

Access Full Text

Single poly-EEPROM with stacked MIM and n-well capacitor

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The new structure of electrically erasable programmable read-only memory (EEPROM), using a capacitor of stacked metal-insulator-metal (MIM) and n-well, is proposed. The oxide capacitance in the n-well region is effectively applied without sacrificing the cell area and the control gate coupling ratio. Therefore, for the same program-voltage rating, the proposed cell allows the EEPROM to have a higher speed handling capability even with a quite small cell size. Measured results show that the programming speed of the proposed cell is almost the same as that of the conventional MIM control gate cell. In an endurance test of 10 000 program/erase cycles, the shift of program threshold voltage is found to be 1.4 V without degradation of read currents.

Inspec keywords: capacitors; EPROM; MIM devices

Other keywords: program-voltage rating; metal-insulator-metal; electrically erasable programmable read-only memory; gate coupling ratio; stacked MIM; single poly-EEPROM; n-well capacitor

Subjects: Semiconductor storage; Capacitors; Metal-insulator-metal and metal-semiconductor-metal structures; Memory circuits

References

    1. 1)
    2. 2)
    3. 3)
      • K. Ohsaki , N. Asamoto , S. Takagaki . A single poly EEPROM cell structure for use in standard CMOS processes. IEEE J. Solid-State Circuits , 3 , 331 - 336
    4. 4)
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20091786
Loading

Related content

content/journals/10.1049/el_20091786
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading