Design and electrical simulation of on-chip neural learning based on nanocomponents

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Design and electrical simulation of on-chip neural learning based on nanocomponents

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© The Institution of Engineering and Technology
Published

A neural inspired lookup table for reconfigurable circuits is described and simulated. The design is based on conductive bridge RAM to implement the synapses and carbon nanotube field effect transistors (CNTFET) for the other parts. Electrical simulations demonstrate compatibility between the nanocomponents and show the successful training of a linearly separable logical function NOR3.

Inspec keywords: neural chips; logic gates; field effect transistors; random-access storage; table lookup; nanotube devices; carbon nanotubes; semiconductor device models; nanoelectronics; neural net architecture

Other keywords: CNTFET; on-chip neural learning; carbon nanotube field effect transistors; reconfigurable circuits; neural inspired lookup table; nanocomponents; linearly separable logical function NOR3; electrical simulation; C; conductive bridge RAM

Subjects: Memory circuits; Fullerene, nanotube and related devices; Nanometre-scale semiconductor fabrication technology; Neural net devices; Insulated gate field effect transistors; Semiconductor storage; Logic elements; Logic circuits; Semiconductor device modelling, equivalent circuits, design and testing; Computer architecture; Neural nets (circuit implementations)

References

    1. 1)
      • Widrow, B., Hoff, M.E.: `Adaptive switching circuits', 1960 WESCON Convention Record, Part IV, p. 96–104.
    2. 2)
    3. 3)
      • Kund, M., Beitel, G., Pinnow, C.-U., Rohr, T., Schumann, J., Symanczyk, R., Ufert, K., Muller, G.: `Conductive bridging RAM (CBRAM): an emerging non-volatile memory technology scalable to sub 20 nm', IEEE Int. Electron Devices Meeting, 2005, IEDM Tech. Dig., December 2005, p. 754–757.
    4. 4)
    5. 5)
      • Maneux, C., Goguet, J., Fregonese, S., Zimmer, T., D'Honincthun, H.C., Galdin-Retailleau, S.: `Analysis of CNTFET physical compact model', Int. Conf. on Design and Test of Integrated Systems in Nanoscale Technology (DTIS), 2006, p. 40–45.
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