Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Sub-1 V embedded SRAM with bit-error immune dual-boosted cell technique

Sub-1 V embedded SRAM with bit-error immune dual-boosted cell technique

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A sub-1 V operating SRAM based on the dual-boosted cell technique is described. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin (SNM) to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell readout current. A 0.18 µm 256 kbit SRAM macro has been fabricated with the proposed technique, which demonstrated: 0.8 V operation with 50 MHz while consuming a power of 65 µW/MHz; 400 mV read SNM at 0.8 V power supply; and a reduction by 87% in bit-error rate compared with that of a conventional SRAM.

References

    1. 1)
    2. 2)
    3. 3)
    4. 4)
    5. 5)
    6. 6)
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20073298
Loading

Related content

content/journals/10.1049/el_20073298
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address