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Average interconnection delay estimation for on-FPGA communication links

Average interconnection delay estimation for on-FPGA communication links

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A new method is presented, and an analytical expression is derived, for average interconnection delay estimation. This method is directly applicable to predicting the average delay for high-bandwidth communication links implemented on FPGAs. The theoretical results are compared with the measured data from the actual circuits and an average error of 4.6% is reported.

References

    1. 1)
      • IBM: ‘Coreconnect(tm) bus architecture’ White paper, 1999.
    2. 2)
    3. 3)
      • Manohararajah, V.: `Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow', Proc. Workshop on System Level Interconnect Prediction, March 2006, Munich, Germany, p. 3–8.
    4. 4)
    5. 5)
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20071342
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