A four-valued memory circuit using the three-peak MOS-NDR circuit as the driver and a current source as the load is demonstrated. The fabrication of the circuit is based on the standard 0.35 µm CMOS process.
Inspec keywords: negative resistance circuits; CMOS memory circuits; driver circuits; constant current sources
Other keywords:
Subjects: CMOS integrated circuits; Memory circuits; Semiconductor storage; Power electronics, supply and supervisory circuits
References
-
-
1)
- S.J. Wei , H.C. Lin . Multivalued SRAM cell using resonant tunneling diodes. IEEE J. Solid-State Circuits , 212 - 216
-
2)
- A.C. Seabaugh , Y.C. Kao , H.T. Yuan . Nine-state resonant tunneling diode memory. IEEE Electron Device Lett. , 479 - 481
-
3)
- A.F. Gonzalez , M. Bhattacharya , S. Kulkarni , P. Mazumder . CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differential-resistance devices. IEEE J. Solid-State Circuits , 924 - 932
-
4)
- S. Sen , F. Capasso , A.Y. Cho , D. Sivco . Resonant tunneling device with multiple negative differential resistance: digital and signal processing applications with reduced circuit complexity. IEEE Trans. Electron Devices , 2185 - 2191
-
5)
- C.Y. Wu , K.N. Lai . Integrated Λ-type differential negative resistance MOSFET device. IEEE J. Solid-State Circuits , 1094 - 1101
-
6)
- S. Choi , B. Lee , T. Kim , K. Yang . CML-type monostable bistable logic element (MOBILE) using InP-based monolithic RTD/HBT technology. Electron. Lett. , 792 - 793
-
1)
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20063634
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content/journals/10.1049/el_20063634
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