Safe design for TF-SOI power MOSFETs

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Safe design for TF-SOI power MOSFETs

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The aim of the work reported is to establish new design restrictions for thin-film silicon-on-insulator (TF-SOI) power MOSFETs using an analytical closed form expression to obtain the electric field at the gate edge. When the gate oxide is extended above the drift region, this field becomes stronger, thus degrading device performance and reliability.

Inspec keywords: silicon-on-insulator; power MOSFET; semiconductor device models; thin film transistors

Other keywords: TF-SOI power MOSFET; analytical closed form expression; gate oxide; thin-film silicon-on-insulator power MOSFET; drift region; gate edge field

Subjects: Semiconductor device modelling, equivalent circuits, design and testing; Insulated gate field effect transistors; Power semiconductor devices

References

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      • A. Vandoreen , J.F. Conley , S. Cristoloveanu , M. Mojarradi , E. Kolawa . Degradation mechanisms in SOI n-channel LDMOSFETs. Microelectron. Eng. , 489 - 495
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http://iet.metastore.ingenta.com/content/journals/10.1049/el_20063220
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