Dual-channel bootstrapped switch for high-speed high-resolution sampling

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Dual-channel bootstrapped switch for high-speed high-resolution sampling

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A novel low-voltage CMOS bootstrapped switch has been designed. In this switch, a PMOS-type bootstrapped circuit combining with an NMOS-type one forms a dual-channel sampling switch that transmits the input signals to the output. Because of this parallel structure, the variation of on-resistance, owing to the variation of the gate overdrive and the threshold voltage, is greatly reduced, exhibiting gain in the sample-and-hold accuracy and linearity. The design was realised in an SMIC 0.18 µm CMOS process and its greatly improved dynamic performance was measured.

Inspec keywords: bootstrap circuits; sample and hold circuits; integrated circuit design; low-power electronics; semiconductor switches; CMOS integrated circuits

Other keywords: 0.18 micron; PMOS-type bootstrapped circuit; dual-channel bootstrapped switch; CMOS integrated circuit; integrated circuit design; sample-and-hold accuracy; CMOS bootstrapped switch; sample-and-hold linearity

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; Relays and switches; CMOS integrated circuits; Other analogue circuits

References

    1. 1)
      • A.M. Abo , P.R. Gray . A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J. Solid-State Circuits , 599 - 606
    2. 2)
      • Yang, C.Y., Hung, C.C.: `A low-voltage low-distortion MOS sampling switch', IEEE Proc. Int. Symp. Circuits and Systems, 2005, Kobe, Japan, 5, p. 3131–3134.
    3. 3)
      • Fayomi, C.J.B., Roberts, G.W., Sawan, M.: `Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization', IEEE Proc. Int. Symp. Circuits and Systems, 2005, Kobe, Japan, 5, p. 2200–2203.
    4. 4)
      • Ong, A.K.: `A method for reducing the variation in ‘on’ resistance of a MOS sampling switch', IEEE Proc. Int. Symp. Circuits and Systems, 2000, 5, p. 437–440.
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