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Compact low-voltage CMOS four-quadrant analogue multiplier

Compact low-voltage CMOS four-quadrant analogue multiplier

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A compact architecture for a four-quadrant analogue multiplier circuit is presented. The circuit is formed by connecting common source amplifiers with a pair of differential flipped voltage followers. This results in a novel cancellation of the nonlinear terms in the sub-currents, leading to the desired four-quadrant analogue multiplier. The circuit combines low complexity with low-voltage operation and low static power consumption. Simulated results using a 0.35 µm CMOS process are provided.

References

    1. 1)
      • R.G. Cavajal , J. Ramirez-Angulo , A.J. Lopez-Martin , A. Torralba , J.A. Gomez Galen , A. Carlosena , F.M. Chavero . The flipped voltage follower: a useful cell for low-voltage low-power circuit design. IEEE Trans. Circuits Syst. I , 7 , 1276 - 1291
    2. 2)
      • Ramirez Angulo, J., Cavajal, R.G., Matinez-Heredia, J.: `1.4-V supply, wide swing, high-frequency CMOS analogue multiplier with high current efficiency', Proc IEEE ISCAS, May 2000, Geneva, Switzerland, V, p. 553–536.
    3. 3)
    4. 4)
      • Sawigun, C., Mahattanakul, J.: `A low-voltage CMOS linear transconductor suitable for analogue multiplier application', Proc. IEEE ISCAS, May 2006, Greece, p. 1543–1546.
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