http://iet.metastore.ingenta.com
1887

Stable passivation technique for high-temperature polycrystalline silicon on insulator MOSFETs for MEMS integration

Stable passivation technique for high-temperature polycrystalline silicon on insulator MOSFETs for MEMS integration

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A passivation technique is reported based on selective doping of the polycrystalline silicon grain boundaries with phosphorus. The polycrystalline silicon on insulator (PSOI) MOSFETs fabricated on films passivated by this method show considerable improvement in the overall performance compared with unpassivated devices. This technique is compatible with high-temperature micro-electromechanical systems (MEMS) processes and hence can be used to integrate PSOI MOSFETs with MEMS structures and devices.

References

    1. 1)
      • H. Mohfoz-Kotb , A.C. Salaün , T. Mohammed-Brahim , O. Bonnaud . Air-gap polycrystalline silicon thin-film transistors for fully integrated sensors. IEEE Electron Device Lett. , 3 , 165 - 167
    2. 2)
      • E.M. Chow , J.P. Lu , J. Ho , C. Shih , D. De Bruyker , M. Rosa , E. Peeters . High voltage thin film transistors integrated with MEMS. Sens. Actuators A
    3. 3)
      • R.W. Young , B.L. Draper . Integrated field effect transistors for microelectromechanical systems applications, modelling and results. J. Vac. Sci. Technol. B. , 3 , 1032 - 1035
    4. 4)
      • J.F. Nijs , H. Pattyn , K. Baert . Low temperature Poly-Si technologies and comparison with high temperature poly-Si processes. IEE Coll. on Poly-Si Devices and Applications , 16/1 - 16/3
    5. 5)
    6. 6)
    7. 7)
    8. 8)
      • R.J. Daniel , K.N. Bhat , E. Bhattacharya . Effect of doping concentration on the grain boundary trap density and threshold voltage of polycrystalline SOI MOSFETs. Microelectron. Eng. , 2 , 252 - 258
    9. 9)
      • K.N. Bhat , M.C. Ramesh , P.R.S. Rao , B. Ganesh . Polysilicon technology. IETE J. Res. , 143 - 154
    10. 10)
      • J. Levinson , F.R. Shepherd , P.J. Scanlon , W.D. Westwood , G. Este , M. Rider . Conductivity behavior in polycrystalline semiconductor thin-film transistor. J. Appl. Phys. , 2 , 1193 - 1202
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20060480
Loading

Related content

content/journals/10.1049/el_20060480
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address