Optimising data layout for delay-line memory

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Optimising data layout for delay-line memory

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Published

All-optical programmable logic must use recirculating delay lines for storage. Two approaches to minimising the latency inherent in delay-line-based systems by treating the layout of code and data in memory as an integer linear programming (ILP) problem are presented. It is shown that, although this approach can generate optimal code for small routines, it will not scale enough to compile useful programs.

Inspec keywords: optical logic; logic programming; optical storage; optical delay lines; program compilers; integer programming; linear programming; programmable logic devices

Other keywords: ILP; all-optical programmable logic; data layout optimisation; recirculating delay lines; delay-line memory; optical logic gates; integer programming; integer linear programming

Subjects: Optical storage; Optical logic elements; Logic programming; Compilers, interpreters and other processors; Optical storage and retrieval; Optical logic devices and optical computing techniques

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